Tests: Prefer single quotes for regex

Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes).  Necessitates also changing single quotes to `.`, i.e match any.
For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.

examples/smtbmc/glift/mux2.ys

@@ -1,9 +1,9 @@
 logger -expect log "SAT proof finished - no model found: SUCCESS!" 1
-logger -expect log "Number of cells:.*[\t ]12" 1
-logger -expect log "Number of cells:.*[\t ]20" 1
-logger -expect log "Problem is satisfiable with \\gate.__glift_weight = 11." 1
-logger -expect log "Problem is NOT satisfiable with \\gate.__glift_weight <= 10." 1
-logger -expect log "Wire \\gate.__glift_weight is minimized at 11." 1
+logger -expect log 'Number of cells:.*[\t ]12' 1
+logger -expect log 'Number of cells:.*[\t ]20' 1
+logger -expect log 'Problem is satisfiable with \\gate.__glift_weight = 11.' 1
+logger -expect log 'Problem is NOT satisfiable with \\gate.__glift_weight <= 10.' 1
+logger -expect log 'Wire \\gate.__glift_weight is minimized at 11.' 1
 logger -expect log "Specializing .* from file with .* = 1." 2
 logger -expect log "Specializing .* from file with .* = 0." 4
 read_verilog <<EOT

tests/arch/xilinx/abc9_dff.ys

@@ -1,5 +1,5 @@
-logger -nowarn "Yosys has only limited support for tri-state logic at the moment\. .*"
-logger -nowarn "Ignoring boxed module .*\."
+logger -nowarn "Yosys has only limited support for tri-state logic at the moment. .*"
+logger -nowarn "Ignoring boxed module .*."
 
 read_verilog <<EOT
 module top(input C, D, output [7:0] Q);
@@ -53,10 +53,10 @@ FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
 FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
 endmodule
 EOT
-logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
-logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
-logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
-logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning 'Whitebox .\$paramod\\FDRE\\INIT=.*1. with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\.' 1
+logger -expect warning 'Whitebox .\$paramod\\FDRE_1\\INIT=.*1. with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\.' 1
+logger -expect warning 'Whitebox .FDSE. with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\.' 1
+logger -expect warning 'Whitebox .\$paramod\\FDSE_1\\INIT=.*1. with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\.' 1
 read_verilog -lib +/xilinx/cells_sim.v
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt

tests/scripts/space_in_name.ys

@@ -4,12 +4,13 @@ logger -expect-no-warnings
 logger -expect log "quoted space" 1
 logger -expect log "quoted" 2
 logger -expect log "space" 2
-logger -expect log '\\"escaped' 1
-logger -expect log 'quotes\\"' 1
+logger -expect log '"escaped' 2
+logger -expect log 'quotes"' 2
 
 test_args unquoted space
 test_args "quoted space"
-test_args \"escaped quotes\"
+test_args "\"escaped quotes\""
+test_args '"escaped quotes"'
 
 logger -check-expected
 

tests/select/boxes_import.ys

@@ -24,6 +24,6 @@ select -assert-mod-count 2 =*
 
 logger -check-expected
 
-logger -expect warning "Selection .wb. did not match any module\." 1
-logger -expect error "No top module found in source design\." 1
+logger -expect warning "Selection .wb. did not match any module." 1
+logger -expect error "No top module found in source design." 1
 design -import read -as new_wb wb

tests/select/unset.ys

@@ -6,5 +6,5 @@ EOT
 select -set foo w:*
 select -assert-any @foo
 select -unset foo
-logger -expect error "Selection '\\foo' does not exist!" 1
+logger -expect error 'Selection .\\foo. does not exist!' 1
 select -unset foo

tests/svtypes/typedef_initial_and_assign.ys

@@ -1,12 +1,12 @@
 logger -expect-no-warnings
-logger -expect warning "reg '\\var_12' is assigned in a continuous assignment" 1
-logger -expect warning "reg '\\var_13' is assigned in a continuous assignment" 1
-logger -expect warning "reg '\\var_14' is assigned in a continuous assignment" 1
-logger -expect warning "reg '\\var_15' is assigned in a continuous assignment" 1
-logger -expect warning "reg '\\var_16' is assigned in a continuous assignment" 1
-logger -expect warning "reg '\\var_17' is assigned in a continuous assignment" 1
-logger -expect warning "reg '\\var_18' is assigned in a continuous assignment" 1
-logger -expect warning "reg '\\var_19' is assigned in a continuous assignment" 1
+logger -expect warning 'reg .\\var_12. is assigned in a continuous assignment' 1
+logger -expect warning 'reg .\\var_13. is assigned in a continuous assignment' 1
+logger -expect warning 'reg .\\var_14. is assigned in a continuous assignment' 1
+logger -expect warning 'reg .\\var_15. is assigned in a continuous assignment' 1
+logger -expect warning 'reg .\\var_16. is assigned in a continuous assignment' 1
+logger -expect warning 'reg .\\var_17. is assigned in a continuous assignment' 1
+logger -expect warning 'reg .\\var_18. is assigned in a continuous assignment' 1
+logger -expect warning 'reg .\\var_19. is assigned in a continuous assignment' 1
 
 read_verilog -sv typedef_initial_and_assign.sv
 hierarchy; proc; opt; async2sync

tests/various/printattr.ys

@@ -1,5 +1,5 @@
 logger -expect log ".*cells_not_processed=[01]* .*" 1
-logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1
+logger -expect log '.*src=.<<EOT:1\.1-9\.10. .*' 1
 read_verilog <<EOT
 module mux2(a, b, s, y);
 	input a, b, s;

tests/various/src.ys

@@ -1,5 +1,5 @@
-logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1
-logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1
+logger -expect warning 'wire .\\o. is assigned in a block at <<EOT:2.11-2.17' 1
+logger -expect warning 'wire .\\p. is assigned in a block at <<EOT:3.11-3.16' 1
 read_verilog <<EOT
 module top(input i, output o, p);
 always @* o <= i;

tests/various/sta.ys

@@ -11,7 +11,7 @@ buffer b(.i(i), .o(w));
 endmodule
 EOT
 
-logger -expect warning "Critical-path does not terminate in a recognised endpoint\." 1
+logger -expect warning "Critical-path does not terminate in a recognised endpoint." 1
 sta
 
 
@@ -22,7 +22,7 @@ assign o = i;
 endmodule
 EOT
 
-logger -expect log "No timing paths found\." 1
+logger -expect log "No timing paths found." 1
 sta
 
 
@@ -56,7 +56,7 @@ const0 c(.o(p));
 endmodule
 EOT
 
-logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1
+logger -expect warning "Cell type 'const0' not recognised! Ignoring." 1
 sta
 
 

tests/various/stat.ys

@@ -9,7 +9,7 @@ module \top
   end
 end
 EOT
-logger -expect log "Chip area for module '\\top': 9.072000" 1
+logger -expect log 'Chip area for module .\\top.: 9.072000' 1
 logger -expect-no-warnings
 logger -expect log "        1    9.072 cells" 1
 logger -expect log "        1    9.072   sg13g2_and2_1" 1
@@ -70,7 +70,7 @@ module \child
 
 end
 EOT
-logger -expect log "Chip area for top module '\\top': 112.492800" 1
+logger -expect log 'Chip area for top module .\\top.: 112.492800' 1
 logger -expect log "of which used for sequential elements: 94.348800" 1
 logger -expect log "2   18.144 cells" 1 
 logger -expect log "4  112.493 cells" 1

tests/various/stat_high_level.ys

@@ -82,9 +82,9 @@ module \child
 
 end
 EOT
-logger -expect log "Chip area for top module '\\top': 66.000000" 1
+logger -expect log 'Chip area for top module .\\top.: 66.000000' 1
 logger -expect log "3     30.5        3     30.5 cells" 1
-logger -expect log "2       51        -        -   \$reduce_xor" 2
+logger -expect log "2       51        -        -   \\$reduce_xor" 2
 logger -expect log "8       66        2        5 cells" 2
 logger -expect-no-warnings
 stat -liberty ./stat_area_by_width.lib -top \top -hierarchy

tests/various/stat_high_level2.ys

@@ -81,8 +81,8 @@ module \child
 end
 EOT
 
-logger -expect log "Chip area for top module '\\top': 80.000000" 1
-logger -expect log "1       12        1       12   \$bmux" 1
+logger -expect log 'Chip area for top module .\\top.: 80.000000' 1
+logger -expect log "1       12        1       12   \\$bmux" 1
 logger -expect log "3     37.5        3     37.5 cells" 1
 logger -expect log "8       80        2        5 cells" 2
 logger -expect-no-warnings

tests/various/sv_defines_mismatch.ys

@@ -1,5 +1,5 @@
 # Check that we spot mismatched brackets
-logger -expect error "Mismatched brackets in macro argument: \[ and }." 1
+logger -expect error "Mismatched brackets in macro argument: \\[ and }." 1
 read_verilog <<EOT
 `define foo(x=[1,2})
 EOT

tests/various/sv_defines_too_few.ys

@@ -1,6 +1,6 @@
 # Check that we don't allow passing too few arguments (and, while we're at it, check that passing "no"
 # arguments actually passes 1 empty argument).
-logger -expect error "Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\)." 1
+logger -expect error 'Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\).' 1
 read_verilog <<EOT
 `define foo(x=1, y)
 `foo()

tests/verilog/always_comb_latch_1.ys

@@ -9,5 +9,5 @@ always_comb begin
 end
 endmodule
 EOF
-logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
+logger -expect error '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y. from always_comb process' 1
 proc

tests/verilog/always_comb_latch_2.ys

@@ -11,5 +11,5 @@ always_comb begin
 end
 endmodule
 EOF
-logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
+logger -expect error '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y. from always_comb process' 1
 proc

tests/verilog/always_comb_latch_3.ys

@@ -16,5 +16,5 @@ always_comb begin
 end
 endmodule
 EOF
-logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
+logger -expect error '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y. from always_comb process' 1
 proc

tests/verilog/always_comb_latch_4.ys

@@ -13,5 +13,5 @@ always_comb begin
 end
 endmodule
 EOF
-logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y' from always_comb process" 1
+logger -expect error '^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y. from always_comb process' 1
 proc

tests/verilog/block_end_label_only.ys

@@ -1,4 +1,4 @@
-logger -expect error "Begin label missing where end label \(incorrect_name\) was given\." 1
+logger -expect error 'Begin label missing where end label \(incorrect_name\) was given\.' 1
 read_verilog -sv <<EOF
 module top;
 initial

tests/verilog/block_end_label_wrong.ys

@@ -1,4 +1,4 @@
-logger -expect error "Begin label \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+logger -expect error 'Begin label \(correct_name\) and end label \(incorrect_name\) don.t match\.' 1
 read_verilog -sv <<EOF
 module top;
 initial

tests/verilog/block_labels.ys

@@ -15,7 +15,7 @@ module foo2;
 endmodule
 EOT
 
-logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
+logger -expect error 'Begin label \(a\) and end label \(b\) don.t match\.' 1
 read_verilog <<EOT
 module foo3;
 

tests/verilog/bug2493.ys

@@ -1,4 +1,4 @@
-logger -expect error "Failed to detect width for identifier \\genblk1\.y!" 1
+logger -expect error 'Failed to detect width for identifier \\genblk1\.y!' 1
 read_verilog <<EOT
 module top1;
     wire x;

tests/verilog/conflict_assert.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add procedural assertion `\\x' because a signal with the same name was already created" 1
+logger -expect error 'Cannot add procedural assertion `\\x. because a signal with the same name was already created' 1
 read_verilog -sv <<EOT
 module top;
     wire x, y;

tests/verilog/conflict_cell_memory.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add cell `\\x' because a memory with the same name was already created" 1
+logger -expect error 'Cannot add cell `\\x. because a memory with the same name was already created' 1
 read_verilog <<EOT
 module mod;
 endmodule

tests/verilog/conflict_interface_port.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add interface port `\\i' because a signal with the same name was already created" 1
+logger -expect error 'Cannot add interface port `\\i. because a signal with the same name was already created' 1
 read_verilog -sv <<EOT
 interface intf;
     logic x;

tests/verilog/conflict_memory_wire.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add memory `\\x' because a signal with the same name was already created" 1
+logger -expect error 'Cannot add memory `\\x. because a signal with the same name was already created' 1
 read_verilog <<EOT
 module top;
     reg [2:0] x;

tests/verilog/conflict_pwire.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add pwire `\\x' because a signal with the same name was already created" 1
+logger -expect error 'Cannot add pwire `\\x. because a signal with the same name was already created' 1
 read_verilog -pwires <<EOT
 module top;
     wire x;

tests/verilog/conflict_wire_memory.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add signal `\\x' because a memory with the same name was already created" 1
+logger -expect error 'Cannot add signal `\\x. because a memory with the same name was already created' 1
 read_verilog <<EOT
 module top;
     reg [2:0] x [0:0];

tests/verilog/gen_block_end_label_only.ys

@@ -1,4 +1,4 @@
-logger -expect error "Begin label missing where end label \(incorrect_name\) was given\." 1
+logger -expect error 'Begin label missing where end label \(incorrect_name\) was given\.' 1
 read_verilog -sv <<EOF
 module top;
 if (1)

tests/verilog/gen_block_end_label_wrong.ys

@@ -1,4 +1,4 @@
-logger -expect error "Begin label \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+logger -expect error 'Begin label \(correct_name\) and end label \(incorrect_name\) don.t match\.' 1
 read_verilog -sv <<EOF
 module top;
 if (1)

tests/verilog/genblk_port_decl.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot declare module port `\\x' within a generate block\." 1
+logger -expect error 'Cannot declare module port `\\x. within a generate block\.' 1
 read_verilog <<EOT
 module top(x);
     generate

tests/verilog/hidden_decl.ys

@@ -1,4 +1,4 @@
-logger -expect error "Identifier `\\y' is implicitly declared and `default_nettype is set to none" 1
+logger -expect error 'Identifier `\\y. is implicitly declared and `default_nettype is set to none' 1
 read_verilog <<EOT
 `default_nettype none
 module top1;

tests/verilog/macro_unapplied.ys

@@ -8,7 +8,7 @@ EOT
 
 design -reset
 
-logger -expect error "Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'" 1
+logger -expect error "Expected to find '\\(' to begin macro arguments for 'MACRO', but instead found ';'" 1
 read_verilog -sv <<EOT
 `define MACRO(a = 1, b = 2) initial $display("MACRO(a = %d, b = %d)", a, b)
 module top;

tests/verilog/macro_unapplied_newline.ys

@@ -1,4 +1,4 @@
-logger -expect error "Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'" 1
+logger -expect error 'Expected to find .\(. to begin macro arguments for .foo., but instead found .\\x0a.' 1
 read_verilog -sv <<EOT
 `define foo(a=1) (a)
 `foo

tests/verilog/module_end_label.ys

@@ -7,7 +7,7 @@ EOF
 
 design -reset
 
-logger -expect error "Module name \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+logger -expect error 'Module name \(correct_name\) and end label \(incorrect_name\) don.t match\.' 1
 read_verilog -sv <<EOF
 module correct_name;
 localparam X = 1;

tests/verilog/package_end_label.ys

@@ -7,7 +7,7 @@ EOF
 
 design -reset
 
-logger -expect error "Package name \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+logger -expect error 'Package name \(correct_name\) and end label \(incorrect_name\) don.t match\.' 1
 read_verilog -sv <<EOF
 package correct_name;
 localparam X = 1;

tests/verilog/param_no_default_unbound_1.ys

@@ -8,5 +8,5 @@ module top;
 endmodule
 EOF
 
-logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+logger -expect error 'Parameter `\\X. has no default value and has not been overridden!' 1
 hierarchy -top top

tests/verilog/param_no_default_unbound_2.ys

@@ -8,5 +8,5 @@ module top;
 endmodule
 EOF
 
-logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+logger -expect error 'Parameter `\\X. has no default value and has not been overridden!' 1
 hierarchy -top top

tests/verilog/param_no_default_unbound_3.ys

@@ -8,5 +8,5 @@ module top;
 endmodule
 EOF
 
-logger -expect error "Parameter `\\Y' has no default value and has not been overridden!" 1
+logger -expect error 'Parameter `\\Y. has no default value and has not been overridden!' 1
 hierarchy -top top

tests/verilog/param_no_default_unbound_4.ys

@@ -8,5 +8,5 @@ module top;
 endmodule
 EOF
 
-logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+logger -expect error 'Parameter `\\X. has no default value and has not been overridden!' 1
 hierarchy -top top

tests/verilog/param_no_default_unbound_5.ys

@@ -8,5 +8,5 @@ module top;
 endmodule
 EOF
 
-logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+logger -expect error 'Parameter `\\X. has no default value and has not been overridden!' 1
 hierarchy -top top

tests/verilog/string-literals.ys

@@ -146,7 +146,7 @@ logger -check-expected
 design -reset
 
 # Test octal escape out of range.
-logger -expect warning "octal escape exceeds \\377" 1
+logger -expect warning 'octal escape exceeds \\377' 1
 read_verilog << EOF
 module top;
 	wire[7:0] x = "\400";
@@ -156,7 +156,7 @@ logger -check-expected
 design -reset
 
 # Test invalid octal digit.
-logger -expect warning "'\?' not a valid digit in octal escape sequence" 1
+logger -expect warning "'\\?' not a valid digit in octal escape sequence" 1
 read_verilog << EOF
 module top;
 	wire[7:0] x = "\0?";

tests/verilog/wire_and_var.ys

@@ -1,9 +1,9 @@
-logger -expect warning "wire '\\wire_1' is assigned in a block" 1
-logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1
+logger -expect warning 'wire .\\wire_1. is assigned in a block' 1
+logger -expect warning 'reg .\\reg_2. is assigned in a continuous assignment' 1
 
-logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1
+logger -expect warning 'reg .\\var_reg_2. is assigned in a continuous assignment' 1
 
-logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1
-logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1
+logger -expect warning 'wire .\\wire_logic_1. is assigned in a block' 1
+logger -expect warning 'wire .\\wire_integer_1. is assigned in a block' 1
 
 read_verilog -sv wire_and_var.sv