3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-09 09:21:58 +00:00
yosys/tests/verilog/always_comb_latch_1.ys
Krystine Sherwin 1248af1e02
Tests: Prefer single quotes for regex
Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes).  Necessitates also changing single quotes to `.`, i.e match any.
For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.
2025-10-06 14:22:33 +13:00

13 lines
243 B
Text

read_verilog -sv <<EOF
module top;
logic x;
always_comb begin
logic y;
if (x)
y = 1;
x = y;
end
endmodule
EOF
logger -expect error '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y. from always_comb process' 1
proc