Tests: Prefer single quotes for regex

Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes).  Necessitates also changing single quotes to `.`, i.e match any.
For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.

tests/verilog/always_comb_latch_1.ys

@@ -9,5 +9,5 @@ always_comb begin
 end
 endmodule
 EOF
-logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
+logger -expect error '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y. from always_comb process' 1
 proc

tests/verilog/always_comb_latch_2.ys

@@ -11,5 +11,5 @@ always_comb begin
 end
 endmodule
 EOF
-logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
+logger -expect error '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y. from always_comb process' 1
 proc

tests/verilog/always_comb_latch_3.ys

@@ -16,5 +16,5 @@ always_comb begin
 end
 endmodule
 EOF
-logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
+logger -expect error '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y. from always_comb process' 1
 proc

tests/verilog/always_comb_latch_4.ys

@@ -13,5 +13,5 @@ always_comb begin
 end
 endmodule
 EOF
-logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y' from always_comb process" 1
+logger -expect error '^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y. from always_comb process' 1
 proc

tests/verilog/block_end_label_only.ys

@@ -1,4 +1,4 @@
-logger -expect error "Begin label missing where end label \(incorrect_name\) was given\." 1
+logger -expect error 'Begin label missing where end label \(incorrect_name\) was given\.' 1
 read_verilog -sv <<EOF
 module top;
 initial

tests/verilog/block_end_label_wrong.ys

@@ -1,4 +1,4 @@
-logger -expect error "Begin label \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+logger -expect error 'Begin label \(correct_name\) and end label \(incorrect_name\) don.t match\.' 1
 read_verilog -sv <<EOF
 module top;
 initial

tests/verilog/block_labels.ys

@@ -15,7 +15,7 @@ module foo2;
 endmodule
 EOT
 
-logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
+logger -expect error 'Begin label \(a\) and end label \(b\) don.t match\.' 1
 read_verilog <<EOT
 module foo3;
 

tests/verilog/bug2493.ys

@@ -1,4 +1,4 @@
-logger -expect error "Failed to detect width for identifier \\genblk1\.y!" 1
+logger -expect error 'Failed to detect width for identifier \\genblk1\.y!' 1
 read_verilog <<EOT
 module top1;
     wire x;

tests/verilog/conflict_assert.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add procedural assertion `\\x' because a signal with the same name was already created" 1
+logger -expect error 'Cannot add procedural assertion `\\x. because a signal with the same name was already created' 1
 read_verilog -sv <<EOT
 module top;
     wire x, y;

tests/verilog/conflict_cell_memory.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add cell `\\x' because a memory with the same name was already created" 1
+logger -expect error 'Cannot add cell `\\x. because a memory with the same name was already created' 1
 read_verilog <<EOT
 module mod;
 endmodule

tests/verilog/conflict_interface_port.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add interface port `\\i' because a signal with the same name was already created" 1
+logger -expect error 'Cannot add interface port `\\i. because a signal with the same name was already created' 1
 read_verilog -sv <<EOT
 interface intf;
     logic x;

tests/verilog/conflict_memory_wire.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add memory `\\x' because a signal with the same name was already created" 1
+logger -expect error 'Cannot add memory `\\x. because a signal with the same name was already created' 1
 read_verilog <<EOT
 module top;
     reg [2:0] x;

tests/verilog/conflict_pwire.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add pwire `\\x' because a signal with the same name was already created" 1
+logger -expect error 'Cannot add pwire `\\x. because a signal with the same name was already created' 1
 read_verilog -pwires <<EOT
 module top;
     wire x;

tests/verilog/conflict_wire_memory.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot add signal `\\x' because a memory with the same name was already created" 1
+logger -expect error 'Cannot add signal `\\x. because a memory with the same name was already created' 1
 read_verilog <<EOT
 module top;
     reg [2:0] x [0:0];

tests/verilog/gen_block_end_label_only.ys

@@ -1,4 +1,4 @@
-logger -expect error "Begin label missing where end label \(incorrect_name\) was given\." 1
+logger -expect error 'Begin label missing where end label \(incorrect_name\) was given\.' 1
 read_verilog -sv <<EOF
 module top;
 if (1)

tests/verilog/gen_block_end_label_wrong.ys

@@ -1,4 +1,4 @@
-logger -expect error "Begin label \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+logger -expect error 'Begin label \(correct_name\) and end label \(incorrect_name\) don.t match\.' 1
 read_verilog -sv <<EOF
 module top;
 if (1)

tests/verilog/genblk_port_decl.ys

@@ -1,4 +1,4 @@
-logger -expect error "Cannot declare module port `\\x' within a generate block\." 1
+logger -expect error 'Cannot declare module port `\\x. within a generate block\.' 1
 read_verilog <<EOT
 module top(x);
     generate

tests/verilog/hidden_decl.ys

@@ -1,4 +1,4 @@
-logger -expect error "Identifier `\\y' is implicitly declared and `default_nettype is set to none" 1
+logger -expect error 'Identifier `\\y. is implicitly declared and `default_nettype is set to none' 1
 read_verilog <<EOT
 `default_nettype none
 module top1;

tests/verilog/macro_unapplied.ys

@@ -8,7 +8,7 @@ EOT
 
 design -reset
 
-logger -expect error "Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'" 1
+logger -expect error "Expected to find '\\(' to begin macro arguments for 'MACRO', but instead found ';'" 1
 read_verilog -sv <<EOT
 `define MACRO(a = 1, b = 2) initial $display("MACRO(a = %d, b = %d)", a, b)
 module top;

tests/verilog/macro_unapplied_newline.ys

@@ -1,4 +1,4 @@
-logger -expect error "Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'" 1
+logger -expect error 'Expected to find .\(. to begin macro arguments for .foo., but instead found .\\x0a.' 1
 read_verilog -sv <<EOT
 `define foo(a=1) (a)
 `foo

tests/verilog/module_end_label.ys

@@ -7,7 +7,7 @@ EOF
 
 design -reset
 
-logger -expect error "Module name \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+logger -expect error 'Module name \(correct_name\) and end label \(incorrect_name\) don.t match\.' 1
 read_verilog -sv <<EOF
 module correct_name;
 localparam X = 1;

tests/verilog/package_end_label.ys

@@ -7,7 +7,7 @@ EOF
 
 design -reset
 
-logger -expect error "Package name \(correct_name\) and end label \(incorrect_name\) don't match\." 1
+logger -expect error 'Package name \(correct_name\) and end label \(incorrect_name\) don.t match\.' 1
 read_verilog -sv <<EOF
 package correct_name;
 localparam X = 1;

tests/verilog/param_no_default_unbound_1.ys

@@ -8,5 +8,5 @@ module top;
 endmodule
 EOF
 
-logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+logger -expect error 'Parameter `\\X. has no default value and has not been overridden!' 1
 hierarchy -top top

tests/verilog/param_no_default_unbound_2.ys

@@ -8,5 +8,5 @@ module top;
 endmodule
 EOF
 
-logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+logger -expect error 'Parameter `\\X. has no default value and has not been overridden!' 1
 hierarchy -top top

tests/verilog/param_no_default_unbound_3.ys

@@ -8,5 +8,5 @@ module top;
 endmodule
 EOF
 
-logger -expect error "Parameter `\\Y' has no default value and has not been overridden!" 1
+logger -expect error 'Parameter `\\Y. has no default value and has not been overridden!' 1
 hierarchy -top top

tests/verilog/param_no_default_unbound_4.ys

@@ -8,5 +8,5 @@ module top;
 endmodule
 EOF
 
-logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+logger -expect error 'Parameter `\\X. has no default value and has not been overridden!' 1
 hierarchy -top top

tests/verilog/param_no_default_unbound_5.ys

@@ -8,5 +8,5 @@ module top;
 endmodule
 EOF
 
-logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+logger -expect error 'Parameter `\\X. has no default value and has not been overridden!' 1
 hierarchy -top top

tests/verilog/string-literals.ys

@@ -146,7 +146,7 @@ logger -check-expected
 design -reset
 
 # Test octal escape out of range.
-logger -expect warning "octal escape exceeds \\377" 1
+logger -expect warning 'octal escape exceeds \\377' 1
 read_verilog << EOF
 module top;
 	wire[7:0] x = "\400";
@@ -156,7 +156,7 @@ logger -check-expected
 design -reset
 
 # Test invalid octal digit.
-logger -expect warning "'\?' not a valid digit in octal escape sequence" 1
+logger -expect warning "'\\?' not a valid digit in octal escape sequence" 1
 read_verilog << EOF
 module top;
 	wire[7:0] x = "\0?";

tests/verilog/wire_and_var.ys

@@ -1,9 +1,9 @@
-logger -expect warning "wire '\\wire_1' is assigned in a block" 1
-logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1
+logger -expect warning 'wire .\\wire_1. is assigned in a block' 1
+logger -expect warning 'reg .\\reg_2. is assigned in a continuous assignment' 1
 
-logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1
+logger -expect warning 'reg .\\var_reg_2. is assigned in a continuous assignment' 1
 
-logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1
-logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1
+logger -expect warning 'wire .\\wire_logic_1. is assigned in a block' 1
+logger -expect warning 'wire .\\wire_integer_1. is assigned in a block' 1
 
 read_verilog -sv wire_and_var.sv