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Add latch check step.

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nella 2026-06-15 15:09:23 +02:00
parent 7473fcf939
commit 01e2698247
2 changed files with 47 additions and 0 deletions
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tests/various/check_nolatches.ys Normal file
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read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
proc -latches info
select -assert-count 1 t:$dlatch
logger -expect warning "is a latch of type" 1
check -nolatches
logger -check-expected
design -reset
read_verilog <<EOT
module top(input g, d, output reg q);
always @* q = g ? d : 1'b0;
endmodule
EOT
proc
check -nolatches -assert
design -reset
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
proc -latches info
logger -expect error "Found 1 problems in" 1
check -nolatches -assert