diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index 426216800..479b2ee81 100644
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -60,6 +60,11 @@ struct CheckPass : public Pass {
 		log("        also check for internal cells that have not been mapped to cells of the\n");
 		log("        target architecture\n");
 		log("\n");
+		log("    -nolatches\n");
+		log("        also check for latch cells ($dlatch, $adlatch, $dlatchsr and their\n");
+		log("        $_DLATCH_*/$_DLATCHSR_* mappings) remaining in the design. Use this\n");
+		log("        before techmapping in flows that must not emit latches.\n");
+		log("\n");
 		log("    -allow-tbuf\n");
 		log("        modify the -mapped behavior to still allow $_TBUF_ cells\n");
 		log("\n");
@@ -79,6 +84,7 @@ struct CheckPass : public Pass {
 		bool noinit = false;
 		bool initdrv = false;
 		bool mapped = false;
+		bool nolatches = false;
 		bool allow_tbuf = false;
 		bool assert_mode = false;
 		bool force_detailed_loop_check = false;
@@ -98,6 +104,10 @@ struct CheckPass : public Pass {
 				mapped = true;
 				continue;
 			}
+			if (args[argidx] == "-nolatches") {
+				nolatches = true;
+				continue;
+			}
 			if (args[argidx] == "-allow-tbuf") {
 				allow_tbuf = true;
 				continue;
@@ -265,6 +275,12 @@ struct CheckPass : public Pass {
 				cell_allowed:;
 				}
 
+				if (nolatches && (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) ||
+						cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_"))) {
+					log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape());
+					counter++;
+				}
+
 				for (auto &conn : cell->connections()) {
 					bool input = cell->input(conn.first);
 					bool output = cell->output(conn.first);
diff --git a/tests/various/check_nolatches.ys b/tests/various/check_nolatches.ys
new file mode 100644
index 000000000..fc981603f
--- /dev/null
+++ b/tests/various/check_nolatches.ys
@@ -0,0 +1,31 @@
+read_verilog <<EOT
+module top(input g, rn, d, output reg q);
+always @* if (~rn) q <= 0; else if (g) q <= d;
+endmodule
+EOT
+proc -latches info
+select -assert-count 1 t:$dlatch
+logger -expect warning "is a latch of type" 1
+check -nolatches
+logger -check-expected
+
+design -reset
+
+read_verilog <<EOT
+module top(input g, d, output reg q);
+always @* q = g ? d : 1'b0;
+endmodule
+EOT
+proc
+check -nolatches -assert
+
+design -reset
+
+read_verilog <<EOT
+module top(input g, rn, d, output reg q);
+always @* if (~rn) q <= 0; else if (g) q <= d;
+endmodule
+EOT
+proc -latches info
+logger -expect error "Found 1 problems in" 1
+check -nolatches -assert