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https://github.com/YosysHQ/yosys
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Add latch inference msg severity option.
This commit is contained in:
nella
parent
8869ce61dc
commit
7473fcf939
4 changed files with 97 additions and 7 deletions
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@ -69,10 +69,14 @@ struct ProcPass : public Pass {
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log(" -noopt\n");
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log(" Will omit the opt_expr pass.\n");
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log("\n");
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log(" -latches <auto|warn|error>\n");
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log(" controls how the inference of a latch is reported.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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std::string global_arst;
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std::string latches;
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bool ifxmode = false;
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bool nomux = false;
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bool noopt = false;
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@ -104,6 +108,10 @@ struct ProcPass : public Pass {
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norom = true;
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continue;
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}
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if (args[argidx] == "-latches" && argidx+1 < args.size()) {
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latches = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -121,7 +129,10 @@ struct ProcPass : public Pass {
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Pass::call(design, "proc_rom");
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if (!nomux)
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Pass::call(design, ifxmode ? "proc_mux -ifx" : "proc_mux");
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Pass::call(design, "proc_dlatch");
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if (latches.empty())
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Pass::call(design, "proc_dlatch");
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else
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Pass::call(design, "proc_dlatch -latches " + latches);
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Pass::call(design, "proc_dff");
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Pass::call(design, "proc_memwr");
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Pass::call(design, "proc_clean");
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@ -345,7 +345,13 @@ struct proc_dlatch_db_t
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}
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};
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void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
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enum LatchPolicy {
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POLICY_AUTO,
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POLICY_WARN,
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POLICY_ERROR
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};
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void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy)
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{
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RTLIL::SigSig latches_bits, nolatches_bits;
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dict<SigBit, SigBit> latches_out_in;
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@ -443,6 +449,12 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
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if (proc->get_bool_attribute(ID::always_comb))
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log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n",
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db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
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else if (policy == POLICY_ERROR)
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log_error("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
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db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
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else if (policy == POLICY_WARN)
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log_warning("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
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db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
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else
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log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
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db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
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@ -458,22 +470,49 @@ struct ProcDlatchPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" proc_dlatch [selection]\n");
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log(" proc_dlatch [options] [selection]\n");
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log("\n");
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log("This pass identifies latches in the processes and converts them to\n");
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log("d-type latches.\n");
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log("\n");
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log(" -latches <auto|warn|error>\n");
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log(" controls how the inference of a latch is reported. Alternatively, one\n");
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log(" can use the 'proc.latches' scratchpad variable.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n");
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extra_args(args, 1, design);
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std::string policy_str;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-latches" && argidx+1 < args.size()) {
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policy_str = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (policy_str.empty())
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policy_str = design->scratchpad_get_string("proc.latches", "warn");
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LatchPolicy policy;
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if (policy_str == "auto")
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policy = POLICY_AUTO;
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else if (policy_str == "warn")
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policy = POLICY_WARN;
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else if (policy_str == "error")
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policy = POLICY_ERROR;
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else
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log_cmd_error("Invalid value '%s' for -latches (expected auto|warn|error).\n", policy_str.c_str());
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for (auto mod : design->all_selected_modules()) {
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proc_dlatch_db_t db(mod);
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for (auto proc : mod->selected_processes())
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proc_dlatch(db, proc);
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proc_dlatch(db, proc, policy);
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db.fixup_muxes();
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}
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}
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@ -78,6 +78,9 @@ struct SynthPass : public ScriptPass {
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log(" -nordff\n");
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log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n");
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log("\n");
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log(" -latches <auto|warn|error>\n");
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log(" controls how the inference of a latch is reported.\n");
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log("\n");
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log(" -noshare\n");
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log(" do not run SAT-based resource sharing\n");
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log("\n");
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@ -111,7 +114,7 @@ struct SynthPass : public ScriptPass {
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log("\n");
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}
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string top_module, fsm_opts, memory_opts, abc;
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string top_module, fsm_opts, memory_opts, abc, latches_opt;
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bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, arith_tree, hieropt, relative_share;
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int lut;
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std::vector<std::string> techmap_maps;
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@ -121,6 +124,7 @@ struct SynthPass : public ScriptPass {
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top_module.clear();
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fsm_opts.clear();
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memory_opts.clear();
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latches_opt.clear();
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autotop = false;
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flatten = false;
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@ -200,6 +204,10 @@ struct SynthPass : public ScriptPass {
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memory_opts += " -nordff";
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continue;
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}
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if (args[argidx] == "-latches" && argidx + 1 < args.size()) {
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latches_opt += " -latches " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-noshare") {
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noshare = true;
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continue;
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@ -276,7 +284,7 @@ struct SynthPass : public ScriptPass {
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}
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if (check_label("coarse")) {
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run("proc");
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run("proc" + latches_opt);
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if (flatten || help_mode) {
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run("check");
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run("flatten", " (if -flatten)");
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32
tests/proc/proc_latches.ys
Normal file
32
tests/proc/proc_latches.ys
Normal file
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@ -0,0 +1,32 @@
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# warn
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read_verilog <<EOT
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module top(input g, rn, d, output reg q);
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always @* if (~rn) q <= 0; else if (g) q <= d;
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endmodule
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EOT
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logger -expect warning "Latch inferred for signal" 1
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proc
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logger -check-expected
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design -reset
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# auto
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read_verilog <<EOT
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module top(input g, rn, d, output reg q);
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always @* if (~rn) q <= 0; else if (g) q <= d;
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endmodule
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EOT
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logger -expect-no-warnings
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proc -latches auto
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logger -check-expected
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design -reset
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# error
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read_verilog <<EOT
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module top(input g, rn, d, output reg q);
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always @* if (~rn) q <= 0; else if (g) q <= d;
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endmodule
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EOT
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logger -expect error "Latch inferred for signal" 1
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proc -latches error
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