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sby/tests/regression/verilog_hier_path.sby
2024-10-16 15:05:02 +02:00

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[options]
mode bmc
depth 1
expect fail
[engines]
smtbmc
[script]
read_verilog -formal sub.v
read_verilog -formal top.v
prep -top \\(foo)
[file top.v]
module \\(foo) (input a);
always @* begin
assert_foo: assert (a);
end
\\(bar) \\(bar)=i= (.a(a));
endmodule
[file sub.v]
module \\(bar) (input a);
always @* begin
assert_bar: assert (a);
end
endmodule