d6d7119cd5
w_underfill should provide identical results regardless of whether or not Verific is used. w_overfill doesn't have the extra check for prettiness without Verific because I'm too lazy to do it. Replaced $past function with past_nwen register to ensure correct operation. Expanded w_underfill under Verific to use a property block to more easily compare the two versions side by side. Changed Concurrent assertions section of doc to compare the two implementations of w_underfill. Should provide a better example for why using verific makes it easier. |
||
|---|---|---|
| .github/workflows | ||
| docs | ||
| extern | ||
| sbysrc | ||
| tests | ||
| .gitignore | ||
| .readthedocs.yaml | ||
| COPYING | ||
| Makefile | ||
| README.md | ||
SymbiYosys (sby) is a front-end driver program for Yosys-based formal hardware verification flows. See https://yosyshq.readthedocs.io/projects/sby/ for documentation on how to use SymbiYosys.
SymbiYosys (sby) itself is licensed under the ISC license, note that the solvers and other components used by SymbiYosys come with their own license terms. There is some more details in the "Selecting the right engine" section of the documentation.
SymbiYosys (sby) is part of the Tabby CAD Suite and the OSS CAD Suite! The easiest way to use sby is to install the binary software suite, which contains all required dependencies, including all supported solvers.
- Contact YosysHQ for a Tabby CAD Suite Evaluation License and download link
- OR go to https://github.com/YosysHQ/oss-cad-suite-build/releases to download the free OSS CAD Suite
- Follow the Install Instructions on GitHub
Make sure to get a Tabby CAD Suite Evaluation License for extensive SystemVerilog Assertion (SVA) support, as well as industry-grade SystemVerilog and VHDL parsers!
For more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet.