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18 lines
648 B
Verilog
18 lines
648 B
Verilog
`default_nettype none
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module module1 (input wire active, output wire tri_out);
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assign tri_out = active ? 1'b0 : 1'bz;
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endmodule
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module module2 (input wire active, output wire tri_out);
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assign tri_out = active ? 1'b0 : 1'bz;
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endmodule
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module top_pass (input wire clk, input wire active1, output wire out);
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module1 module1 (.active(active1), .tri_out(out));
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module2 module2 (.active(!active1), .tri_out(out));
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endmodule
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module top_fail (input wire clk, input wire active1, input wire active2, output wire out);
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module1 module1 (.active(active1), .tri_out(out));
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module2 module2 (.active(active2), .tri_out(out));
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endmodule
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