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sby/docs/examples/demos/fib.sby
Clifford Wolf 951211856d Add fib example using tasks
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-06 00:03:54 +01:00

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[tasks]
cover
prove
live
[options]
cover: mode cover
prove: mode prove
live: mode live
[engines]
cover:
smtbmc z3
prove:
abc pdr
live:
aiger suprove
--
[script]
read_verilog -formal fib.v
prep -top fib
[files]
fib.v