Formal extensions to Verilog ============================ TBD ``read -sv`` ``read_verilog -sv`` SystemVerilog Immediate Assertions ---------------------------------- TBD ``assert();`` ``assume();`` ``cover();`` SystemVerilog Functions ----------------------- TBD ``$past`` ``$stable`` ``$rose``, ``$fell`` Liveness and Fairness --------------------- TBD ``assert property (eventually );`` ``assume property (eventually );`` Unconstrained Variables ----------------------- TBD ``(* anyconst *)`` ``(* anyseq *)`` ``(* allconst *)`` ``(* allseq *)`` Global Clock ------------ TBD ``(* gclk *)`` SystemVerilog Concurrent Assertions ----------------------------------- TBD, see :ref:`sva`.