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31 lines
1.4 KiB
Markdown
31 lines
1.4 KiB
Markdown
# Autotune demo
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This directory contains a simple sequential integer divider circuit. The
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verilog implementation in [divider.sv](divider.sv) comes with assertions that
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this circuit will always produce the correct result and will always finish
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within a fixed number of cycles. The circuit has the divider bit-width as
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parameter.
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Increasing the WIDTH parameter quickly turns proving those assertions into a
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very difficult proof for fully autmated solvers. This makes it a good example
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for the `--autotune` option which tries different backend engines to find the
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best performing engine configuration for a given verification task.
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The [divider.sby](divider.sby) file defines 3 tasks named `small`, `medium` and
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`large` which configure the divider with different bit-widths. To verify the
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`small` divider using the default engine run:
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sby -f divider.sby small
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To automatically try different backend engines using autotune, run
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sby --autotune -f divider.sby small
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The `small` task should finish quickly using both the default engine and using
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autotune. The `medium` and `large` tasks take significantly longer and show
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greater differences between engine configurations. Note that the `large` tasks
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can take many minutes to hours, depending on the machine you are using.
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You can learn more about Sby's autotune feature from [Sby's
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documentation](https://symbiyosys.readthedocs.io/en/latest/autotune.html).
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