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Demonstrate binding SVA properties to a VHDL design. Mention example code (with snippets) in section on Verific.
11 lines
243 B
Systemverilog
11 lines
243 B
Systemverilog
module formal_bind(input clk, rst, up, down, [3:0] count);
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initial assume(rst);
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assert property(@(posedge clk) count != 4'd15);
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cover property(@(posedge clk) count == 4'd10);
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endmodule
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bind updowncount formal_bind fb_inst(.*);
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