Krystine Sherwin 549c5f33f5 Add formal_bind example ... Demonstrate binding SVA properties to a VHDL design. Mention example code (with snippets) in section on Verific.		2024-03-05 15:29:08 +13:00
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examples	Add formal_bind example	2024-03-05 15:29:08 +13:00
source	Add formal_bind example	2024-03-05 15:29:08 +13:00
static	Change Sphinx theme to "furo"	2023-05-03 16:56:09 +02:00
.gitignore	update docs theme	2021-11-26 20:34:55 +01:00
Makefile	Initial import	2017-01-22 16:47:47 +01:00