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18 lines
446 B
Systemverilog
18 lines
446 B
Systemverilog
module example(clk, state);
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input logic clk;
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output logic [4:0] state = 27;
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always_ff @(posedge clk) state <= (5'd 2 * state - 5'd 1) ^ (state & 5'd 7);
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let p0 = (state != 0);
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let p1 = (state inside {28, 19, 6, 13});
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let p2 = (state inside {28, 19, 6, 13, 22, 27});
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let p3 = (state[0] & state[1]) ^ state[2];
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`ifdef ASSERT_PX
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always_comb assert (`ASSERT_PX);
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`endif
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`ifdef ASSUME_PX
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always_comb assume (`ASSUME_PX);
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`endif
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endmodule
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