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Code Activity
646 commits 7 branches 26 tags 1.3 MiB
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30 commits

Author SHA1 Message Date
Jannis Harder e0dda21555 abc: Support arbitrary prep abc commands 2024-04-19 16:40:30 +02:00
KrystalDelusion 6c8b838eb3
Update sby_engine_abc.py 
ABC will sometimes return negative frame numbers when proving by convergence, e.g.
```
engine_0: Proved output 1 in frame -698905656 (converged).
engine_0: Proved output 4 in frame -698905656 (converged).
```
This change fixes these properties being missed and causing the engine status to return UNKNOWN due to `proved_count != len(proved)`.
 2024-03-12 10:48:26 +13:00
Jannis Harder b6e41a388b Support for the new anytime schedule in yosys-abc's pdr 2024-03-06 12:26:01 +01:00
Jannis Harder 6ba762db4c Support for "abc --keep-going pdr" via new "pdr -X" mode 2024-02-20 14:06:43 +01:00
Claire Xenia Wolf f692eff845 Add support for "abc pdr -d" engine 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2023-06-07 22:21:06 +02:00
Claire Xenia Wolf 8b3ba68845 Add aigfolds option 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2023-06-07 22:05:17 +02:00
Jannis Harder 6d3b5aa960 Unified trace generation using yosys's sim across all engines 
Currently opt-in using the `fst` or `vcd_sim` options.
 2023-01-10 18:42:26 +01:00
Claire Xenia Wolf 003ccf7197 Add color handling via click.style and click.echo 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-10-31 20:29:32 +01:00
Jannis Harder 966bdae1f6 aigbmc: Convert aiw trace to yw trace and load that into smtbmc 
This handles more edge cases concerning FF initialization, memories and
hierarchy.
 2022-10-20 14:36:07 +02:00
Jannis Harder 168d667b6d Add vcd option to make VCD writing optional 2022-09-05 15:42:24 +02:00
Jannis Harder 92e7eb2e32 abc pdr: Enable log output by default 
This makes it consistent with the other abc solvers and shows whether
abc pdr is making progress.
 2022-07-08 12:36:44 +02:00
Jannis Harder d0c59a3155 Don't use python asserts to handle unexpected solver output 2022-06-15 13:25:21 +02:00
N. Engelhardt 7c9e5b026b Rename SbyJob to SbyTask and SbyTask to SbyProc to reduce confusion. Config file tasks now correspond to SbyTasks. 2022-01-11 17:08:56 +01:00
Claire Xenia Wolf 1b3832cf92 Fixed names and links 2021-10-31 14:42:39 +01:00
piegames 2d7d48885b Turn .format() strings into f-strings 2021-06-26 19:46:30 +02:00
N. Engelhardt 0c0215de91 fix formatting error 2020-04-02 17:21:48 +02:00
N. Engelhardt 30d7c32ec6 Use .format() instead of % 
Signed-off-by: N. Engelhardt <nak@symbioticeda.com>
 2020-03-25 13:09:37 +01:00
Clifford Wolf f2697c23c0 Fixed "counterexample trace:" log message for things like warmup failed 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-21 14:00:30 +02:00
Clifford Wolf 36c7185393 More improvements in sby error handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-27 16:23:57 +02:00
Clifford Wolf 6ef12a4b31 Add tbtop config option 2017-07-01 18:33:36 +02:00
Clifford Wolf ff054ab88b Add support for "aigsmt none" option 2017-05-28 12:32:03 +02:00
Clifford Wolf 7be08218cb Add "append" option 2017-02-26 11:08:14 +01:00
Clifford Wolf eb83a1b90e Add aigsmt option 2017-02-25 15:06:47 +01:00
Clifford Wolf b5be4a5759 Add aiger engine 2017-02-19 23:53:01 +01:00
Clifford Wolf 7085657687 Add options to set tool paths 2017-02-09 14:09:14 +01:00
Clifford Wolf c2c273c7c8 Add "expect" config option 2017-02-06 16:30:29 +01:00
Clifford Wolf b8fefaa25b Improve "abc sim3" handling 2017-02-03 12:17:22 +01:00
Clifford Wolf 1f6037c158 Add support for "abc sim3" engine 2017-02-02 16:59:09 +01:00
Clifford Wolf 5125128bbd Added prove mode support via "abc pdr" 2017-01-30 12:32:49 +01:00
Clifford Wolf 363273df52 Refactor engine/mode interfaces 2017-01-30 11:57:04 +01:00
Renamed from sbysrc/sby_bmc.py (Browse further)