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Add docs/examples/abstract

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-03-27 14:45:30 +01:00
parent f918e2369a
commit afe6960ffe
6 changed files with 124 additions and 0 deletions
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19
docs/examples/abstract/demo.v Normal file
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@ -0,0 +1,19 @@
module demo (
input clock,
input reset,
output A, B, C, D
);
reg [19:0] counter = 0;
always @(posedge clock) begin
if (reset)
counter <= 0;
else
counter <= counter + 1;
end
assign A = counter == 123456;
assign B = counter == 234567;
assign C = counter == 345678;
assign D = counter == 456789;
endmodule