Merge branch 'master' into fifo_example

docs/examples/Makefile

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+SUBDIR=../docs/examples
+TESTDIR=../../tests
+include $(TESTDIR)/make/subdir.mk

docs/examples/abstract/Makefile

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+SUBDIR=../docs/examples/abstract
+TESTDIR=../../../tests
+include $(TESTDIR)/make/subdir.mk

docs/examples/demos/Makefile

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+SUBDIR=../docs/examples/demos
+TESTDIR=../../../tests
+include $(TESTDIR)/make/subdir.mk

docs/examples/demos/memory.sby

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+[options]
+depth 10
+mode bmc
+
+[engines]
+smtbmc yices
+
+[script]
+read_verilog -formal demo.v
+prep -top top
+
+[file demo.v]
+module top (
+  input clk,
+  input [7:0] addr,
+  input [7:0] wdata,
+  output [7:0] rdata
+);
+  rand const reg [7:0] test_addr;
+  reg [7:0] test_data;
+  reg test_valid = 0;
+
+  always @(posedge clk) begin
+    if (addr == test_addr) begin
+      if (test_valid)
+        assert(test_data == rdata);
+      test_data <= wdata;
+      test_valid <= 1;
+    end
+  end
+
+  memory uut (
+    .clk  (clk  ),
+    .addr (addr ),
+    .wdata(wdata),
+    .rdata(rdata)
+  );
+endmodule
+
+
+module memory (
+  input clk,
+  input [7:0] addr,
+  input [7:0] wdata,
+  output [7:0] rdata
+);
+  reg [7:0] mem [0:255];
+
+  always @(posedge clk)
+    mem[addr] <= wdata;
+
+  assign rdata = mem[addr];
+endmodule

docs/examples/demos/picorv32_axicheck.sby

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+[tasks]
+yices
+boolector
+z3
+abc
+
+[options]
+mode bmc
+depth 10
+
+[engines]
+yices: smtbmc yices
+boolector: smtbmc boolector -ack
+z3: smtbmc --nomem z3
+abc: abc bmc3
+
+[script]
+read_verilog -formal -norestrict -assume-asserts picorv32.v
+read_verilog -formal axicheck.v
+prep -top testbench
+
+[files]
+picorv32.v ../../../extern/picorv32.v
+axicheck.v ../../../extern/axicheck.v
+

docs/examples/demos/up_down_counter.sby

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+[tasks]
+suprove
+avy
+
+[options]
+mode prove
+
+[engines]
+suprove: aiger suprove
+avy: aiger avy
+
+[script]
+read_verilog -formal demo.v
+prep -top top
+
+[file demo.v]
+module top(input clk, input up, down);
+  reg [4:0] counter = 0;
+  always @(posedge clk) begin
+    if (up && counter != 10) counter <= counter + 1;
+    if (down && counter != 0) counter <= counter - 1;
+  end
+  assert property (counter != 15);
+endmodule

docs/examples/indinv/Makefile

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+SUBDIR=../docs/examples/indinv
+TESTDIR=../../../tests
+include $(TESTDIR)/make/subdir.mk

docs/examples/multiclk/Makefile

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+SUBDIR=../docs/examples/multiclk
+TESTDIR=../../../tests
+include $(TESTDIR)/make/subdir.mk

docs/examples/puzzles/Makefile

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+SUBDIR=../docs/examples/puzzles
+TESTDIR=../../../tests
+include $(TESTDIR)/make/subdir.mk

docs/examples/quickstart/Makefile

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+SUBDIR=../docs/examples/quickstart
+TESTDIR=../../../tests
+include $(TESTDIR)/make/subdir.mk

docs/examples/tristate/Makefile

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+SUBDIR=../docs/examples/tristate
+TESTDIR=../../../tests
+include $(TESTDIR)/make/subdir.mk

docs/examples/tristate/README.md

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+# Tristate demo
+
+Run 
+
+    sby -f tristate.sby pass
+
+to run the pass task. This uses the top module that exclusively enables each of the submodules.
+
+Run 
+
+    sby -f tristate.sby fail
+
+to run the fail task. This uses the top module that allows submodule to independently enable its tristate outputs.

docs/examples/tristate/tristate.sby

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+[tasks]
+pass
+fail
+
+[options]
+fail: expect fail
+mode prove
+depth 5
+
+[engines]
+smtbmc
+
+[script]
+read -sv tristates.v
+pass: prep -top top_pass
+fail: prep -top top_fail
+flatten; tribuf -formal
+
+[files]
+tristates.v

docs/examples/tristate/tristates.v

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+`default_nettype none
+module module1 (input wire active, output wire tri_out);
+    assign tri_out = active ? 1'b0 : 1'bz;
+endmodule
+
+module module2 (input wire active, output wire tri_out);
+    assign tri_out = active ? 1'b0 : 1'bz;
+endmodule
+
+module top_pass (input wire clk, input wire active1, output wire out);
+    module1 module1 (.active(active1), .tri_out(out));
+    module2 module2 (.active(!active1), .tri_out(out));
+endmodule
+
+module top_fail (input wire clk, input wire active1, input wire active2, output wire out);
+    module1 module1 (.active(active1), .tri_out(out));
+    module2 module2 (.active(active2), .tri_out(out));
+endmodule