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499371fd39
* Rename and move sbysrc/demo[123].sby to docs/examples/demos
* Make them use multiple tasks for multiple engines
* Scan docs/examples for sby files for make test
* `make ci` is now `NOSKIP` by default
* Skip scripts using `verific` w/o yosys verific support
* This does not fail even with NOSKIP set
54 lines
789 B
Plaintext
54 lines
789 B
Plaintext
[options]
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depth 10
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mode bmc
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[engines]
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smtbmc yices
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[script]
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read_verilog -formal demo.v
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prep -top top
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[file demo.v]
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module top (
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input clk,
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input [7:0] addr,
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input [7:0] wdata,
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output [7:0] rdata
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);
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rand const reg [7:0] test_addr;
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reg [7:0] test_data;
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reg test_valid = 0;
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always @(posedge clk) begin
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if (addr == test_addr) begin
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if (test_valid)
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assert(test_data == rdata);
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test_data <= wdata;
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test_valid <= 1;
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end
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end
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memory uut (
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.clk (clk ),
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.addr (addr ),
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.wdata(wdata),
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.rdata(rdata)
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);
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endmodule
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module memory (
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input clk,
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input [7:0] addr,
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input [7:0] wdata,
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output [7:0] rdata
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);
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reg [7:0] mem [0:255];
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always @(posedge clk)
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mem[addr] <= wdata;
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assign rdata = mem[addr];
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endmodule
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