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Fix readme

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Gus Smith 2025-12-15 12:27:24 -08:00
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tests/staged_sim_and_verif/README.md
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@ -4,4 +4,4 @@ Staged simulation + verification example demonstrating staged verification using
- Uses phased SVA (`(* phase = "1" *)`, `(* phase = "2" *)`) and a selector script to strip irrelevant properties per stage.
- Needs Yosys with Verific (`verific -formal` in the scripts).
Run via the wrapper: `make -C tests staged_sim_and_verif/staged_sim_and_verif` (which calls `staged_sim_and_verif.sh` and exercises all four tasks in `skip_staged_flow.sby`).***
Run via the wrapper: from the root directory, call `make -C tests staged_sim_and_verif/staged_sim_and_verif`, which calls `staged_sim_and_verif.sh` and exercises all four tasks in `skip_staged_flow.sby`.