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Gus Smith 2025-12-09 11:20:27 -08:00
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Staged simulation + verification example demonstrating staged verification using simulation and writeback via `sim -w` pass.
- Stage 1: run cover to reach “req sent, ack pending”, producing `trace0.yw`.
- Stage 2: replay the witness with `sim -w` to bake state, then run another cover that requires the ack.
- Uses phased SVA (`(* phase = "1" *)`, `(* phase = "2" *)`) and a selector script to strip irrelevant properties per stage.
- Needs Yosys with Verific (`verific -formal` in the scripts).
Run via the wrapper: `make -C tests staged_sim_and_verif/staged_sim_and_verif` (which calls `staged_sim_and_verif.sh` and exercises all four tasks in `skip_staged_flow.sby`).***