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Fix bitwidths

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Gus Smith 2026-01-21 08:20:00 -08:00
parent fcba8d3780
commit 5e6e984a67
1 changed files with 2 additions and 2 deletions
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4
tests/staged_sim_and_verif/Req_Ack.sv
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@ -6,8 +6,8 @@ module DUT (
`ifdef FORMAL
logic [1:0] reqs_seen;
logic [1:0] acks_seen;
logic [31:0] reqs_seen;
logic [31:0] acks_seen;
logic [31:0] cycle_count;
// Deterministic initial state