diff --git a/tests/staged_sim_and_verif/Req_Ack.sv b/tests/staged_sim_and_verif/Req_Ack.sv
index 52e38aa..c6bd496 100644
--- a/tests/staged_sim_and_verif/Req_Ack.sv
+++ b/tests/staged_sim_and_verif/Req_Ack.sv
@@ -6,8 +6,8 @@ module DUT (
 
 `ifdef FORMAL
 
-        logic [1:0] reqs_seen;
-        logic [1:0] acks_seen;
+        logic [31:0] reqs_seen;
+        logic [31:0] acks_seen;
         logic [31:0] cycle_count;
 
         // Deterministic initial state