Add formal_bind example

Demonstrate binding SVA properties to a VHDL design.
Mention example code (with snippets) in section on Verific.

docs/examples/vhd/formal_bind.sv

@@ -0,0 +1,10 @@
+module formal_bind(input clk, rst, up, down, [3:0] count);
+
+    initial assume(rst);
+
+    assert property(@(posedge clk) count != 4'd15);
+    cover property(@(posedge clk) count == 4'd10);
+
+endmodule
+
+bind updowncount formal_bind fb_inst(.*);