handle unreached cover properties

tests/cover_fail.sby

@@ -0,0 +1,31 @@
+[options]
+mode cover
+depth 5
+expect fail
+
+[engines]
+smtbmc boolector
+
+[script]
+read_verilog -sv test.v
+prep -top test
+
+[file test.v]
+module test(
+input clk,
+input rst,
+output reg [3:0] count
+);
+
+initial assume (rst == 1'b1);
+
+always @(posedge clk) begin
+if (rst)
+  count <= 4'b0;
+else
+  count <= count + 1'b1;
+
+cover (count == 0);
+cover (count == 4'd11);
+end
+endmodule