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32 lines
369 B
Plaintext
32 lines
369 B
Plaintext
[options]
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mode cover
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depth 5
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expect fail
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[engines]
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smtbmc boolector
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[script]
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read_verilog -sv test.v
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prep -top test
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[file test.v]
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module test(
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input clk,
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input rst,
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output reg [3:0] count
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);
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initial assume (rst == 1'b1);
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always @(posedge clk) begin
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if (rst)
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count <= 4'b0;
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else
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count <= count + 1'b1;
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cover (count == 0);
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cover (count == 4'd11);
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end
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endmodule
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