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Regression test for smtbmc --unroll --noincr
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tests/regression/unroll_noincr_traces.sby
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29
tests/regression/unroll_noincr_traces.sby
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[tasks]
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boolector
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yices
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z3
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[options]
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mode bmc
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expect fail
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[engines]
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boolector: smtbmc boolector -- --noincr
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yices: smtbmc --unroll yices -- --noincr
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z3: smtbmc --unroll z3 -- --noincr
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[script]
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read -formal top.sv
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prep -top top
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[file top.sv]
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module top(input clk);
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reg [7:0] counter = 0;
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wire derived = counter * 7;
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always @(posedge clk) begin
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counter <= counter + 1;
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assert (counter < 4);
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end
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endmodule
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