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Extend primegen example

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-03-07 23:10:53 +01:00
parent ec38b0b841
commit 2c13fbefe6
4 changed files with 32 additions and 3 deletions
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12
docs/examples/puzzles/primegen.sby
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@ -1,13 +1,21 @@
[tasks]
primegen
primes_fail
primes_pass
[options]
mode cover
depth 1
primes_fail: expect fail
[engines]
smtbmc --dumpsmt2 --stbv z3
smtbmc --dumpsmt2 --progress --stbv z3
[script]
read_verilog -formal primegen.v
prep -top primegen
primes_fail: chparam -set offset 7 primes
primegen: prep -top primegen
~primegen: prep -top primes
[files]
primegen.v