1616 lines
66 KiB
Plaintext
1616 lines
66 KiB
Plaintext
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 12,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 28,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::r.addr",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::r.en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::r.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::r.data.0",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::r.data.1",
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ty: SInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::w.addr",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::w.en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::w.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::w.data.0",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::w.data.1",
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ty: SInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::w.mask.0",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::w.mask.1",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::r0.addr",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::r0.en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::r0.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1",
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ty: SInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::w1.addr",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::w1.en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::w1.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1",
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ty: SInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1",
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ty: Bool,
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},
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SlotDebugData {
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name: ".0",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: ".1",
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ty: SInt<8>,
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},
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SlotDebugData {
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name: ".0",
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ty: Bool,
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},
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SlotDebugData {
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name: ".1",
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ty: Bool,
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},
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],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 1,
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debug_data: [
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(),
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],
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layout_data: [
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MemoryData {
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array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
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data: [
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// len = 0x10
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[0x0]: 0x2301,
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[0x1]: 0x2301,
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[0x2]: 0x2301,
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[0x3]: 0x2301,
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[0x4]: 0x2301,
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[0x5]: 0x2301,
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[0x6]: 0x2301,
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[0x7]: 0x2301,
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[0x8]: 0x2301,
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[0x9]: 0x2301,
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[0xa]: 0x2301,
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[0xb]: 0x2301,
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[0xc]: 0x2301,
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[0xd]: 0x2301,
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[0xe]: 0x2301,
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[0xf]: 0x2301,
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],
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},
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],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:8:1
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0: Copy {
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dest: StatePartIndex<BigSlots>(17), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.addr", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.addr", ty: UInt<4> },
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},
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1: Copy {
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dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.en", ty: Bool },
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src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.en", ty: Bool },
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},
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2: Copy {
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dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.clk", ty: Clock },
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src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.clk", ty: Clock },
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},
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3: Copy {
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dest: StatePartIndex<BigSlots>(20), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(8), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.data.0", ty: UInt<8> },
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},
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4: Copy {
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dest: StatePartIndex<BigSlots>(21), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1", ty: SInt<8> },
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src: StatePartIndex<BigSlots>(9), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.data.1", ty: SInt<8> },
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},
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5: Copy {
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dest: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0", ty: Bool },
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src: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.mask.0", ty: Bool },
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},
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6: Copy {
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dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1", ty: Bool },
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src: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.mask.1", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:6:1
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7: Copy {
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dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.clk", ty: Clock },
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src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.clk", ty: Clock },
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},
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8: Copy {
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dest: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.en", ty: Bool },
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src: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.en", ty: Bool },
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},
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9: Copy {
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dest: StatePartIndex<BigSlots>(12), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.addr", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(0), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.addr", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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10: CastBigToArrayIndex {
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dest: StatePartIndex<SmallSlots>(9), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(17), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.addr", ty: UInt<4> },
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},
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11: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.en", ty: Bool },
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},
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12: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.clk", ty: Clock },
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},
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13: AndSmall {
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dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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rhs: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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},
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14: CastBigToArrayIndex {
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dest: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(12), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.addr", ty: UInt<4> },
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},
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15: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.en", ty: Bool },
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},
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16: BranchIfSmallZero {
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target: 20,
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value: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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},
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17: MemoryReadUInt {
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dest: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
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memory: StatePartIndex<Memories>(0), // (MemoryData {
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// array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
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// data: [
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// // len = 0x10
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// [0x0]: 0x4050,
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// [0x1]: 0xa090,
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// [0x2]: 0xc0b0,
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// [0x3]: 0x2301,
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// [0x4]: 0x2301,
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// [0x5]: 0x2301,
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// [0x6]: 0x2301,
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// [0x7]: 0x2301,
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// [0x8]: 0x2301,
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// [0x9]: 0x2301,
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// [0xa]: 0x2301,
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// [0xb]: 0x2301,
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// [0xc]: 0x2301,
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// [0xd]: 0x2301,
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// [0xe]: 0x2301,
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// [0xf]: 0x2301,
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// ],
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// }) (),
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addr: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
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stride: 16,
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start: 0,
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width: 8,
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},
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18: MemoryReadSInt {
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dest: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
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memory: StatePartIndex<Memories>(0), // (MemoryData {
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// array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
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// data: [
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// // len = 0x10
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// [0x0]: 0x4050,
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// [0x1]: 0xa090,
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// [0x2]: 0xc0b0,
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// [0x3]: 0x2301,
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// [0x4]: 0x2301,
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// [0x5]: 0x2301,
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// [0x6]: 0x2301,
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// [0x7]: 0x2301,
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// [0x8]: 0x2301,
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// [0x9]: 0x2301,
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// [0xa]: 0x2301,
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// [0xb]: 0x2301,
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// [0xc]: 0x2301,
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// [0xd]: 0x2301,
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// [0xe]: 0x2301,
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// [0xf]: 0x2301,
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// ],
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// }) (),
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addr: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
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stride: 16,
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start: 8,
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width: 8,
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},
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19: Branch {
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target: 22,
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},
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20: Const {
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dest: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
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value: 0x0,
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},
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21: Const {
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dest: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
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value: 0x0,
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},
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// at: module-XXXXXXXXXX.rs:6:1
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22: Copy {
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dest: StatePartIndex<BigSlots>(3), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.data.0", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
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},
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23: Copy {
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dest: StatePartIndex<BigSlots>(4), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.data.1", ty: SInt<8> },
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src: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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24: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.clk", ty: Clock },
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},
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25: AndSmall {
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dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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rhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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},
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26: BranchIfSmallZero {
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target: 27,
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value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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27: BranchIfSmallZero {
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target: 39,
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value: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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28: CopySmall {
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dest: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
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src: StatePartIndex<SmallSlots>(9), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
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},
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29: CopySmall {
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dest: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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30: Copy {
|
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dest: StatePartIndex<BigSlots>(24), // (0xd0) SlotDebugData { name: ".0", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(20), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0", ty: UInt<8> },
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},
|
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31: Copy {
|
|
dest: StatePartIndex<BigSlots>(25), // (-0x20) SlotDebugData { name: ".1", ty: SInt<8> },
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src: StatePartIndex<BigSlots>(21), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1", ty: SInt<8> },
|
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},
|
|
32: Copy {
|
|
dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0", ty: Bool },
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},
|
|
33: Copy {
|
|
dest: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".1", ty: Bool },
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src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1", ty: Bool },
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},
|
|
34: BranchIfSmallZero {
|
|
target: 39,
|
|
value: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
35: BranchIfZero {
|
|
target: 37,
|
|
value: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: Bool },
|
|
},
|
|
36: MemoryWriteUInt {
|
|
value: StatePartIndex<BigSlots>(24), // (0xd0) SlotDebugData { name: ".0", ty: UInt<8> },
|
|
memory: StatePartIndex<Memories>(0), // (MemoryData {
|
|
// array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
|
|
// data: [
|
|
// // len = 0x10
|
|
// [0x0]: 0x4050,
|
|
// [0x1]: 0xa090,
|
|
// [0x2]: 0xc0b0,
|
|
// [0x3]: 0x2301,
|
|
// [0x4]: 0x2301,
|
|
// [0x5]: 0x2301,
|
|
// [0x6]: 0x2301,
|
|
// [0x7]: 0x2301,
|
|
// [0x8]: 0x2301,
|
|
// [0x9]: 0x2301,
|
|
// [0xa]: 0x2301,
|
|
// [0xb]: 0x2301,
|
|
// [0xc]: 0x2301,
|
|
// [0xd]: 0x2301,
|
|
// [0xe]: 0x2301,
|
|
// [0xf]: 0x2301,
|
|
// ],
|
|
// }) (),
|
|
addr: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
|
|
stride: 16,
|
|
start: 0,
|
|
width: 8,
|
|
},
|
|
37: BranchIfZero {
|
|
target: 39,
|
|
value: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".1", ty: Bool },
|
|
},
|
|
38: MemoryWriteSInt {
|
|
value: StatePartIndex<BigSlots>(25), // (-0x20) SlotDebugData { name: ".1", ty: SInt<8> },
|
|
memory: StatePartIndex<Memories>(0), // (MemoryData {
|
|
// array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
|
|
// data: [
|
|
// // len = 0x10
|
|
// [0x0]: 0x4050,
|
|
// [0x1]: 0xa090,
|
|
// [0x2]: 0xc0b0,
|
|
// [0x3]: 0x2301,
|
|
// [0x4]: 0x2301,
|
|
// [0x5]: 0x2301,
|
|
// [0x6]: 0x2301,
|
|
// [0x7]: 0x2301,
|
|
// [0x8]: 0x2301,
|
|
// [0x9]: 0x2301,
|
|
// [0xa]: 0x2301,
|
|
// [0xb]: 0x2301,
|
|
// [0xc]: 0x2301,
|
|
// [0xd]: 0x2301,
|
|
// [0xe]: 0x2301,
|
|
// [0xf]: 0x2301,
|
|
// ],
|
|
// }) (),
|
|
addr: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
|
|
stride: 16,
|
|
start: 8,
|
|
width: 8,
|
|
},
|
|
39: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
40: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
41: Return,
|
|
],
|
|
..
|
|
},
|
|
pc: 41,
|
|
memory_write_log: [],
|
|
memories: StatePart {
|
|
value: [
|
|
MemoryData {
|
|
array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
|
|
data: [
|
|
// len = 0x10
|
|
[0x0]: 0x4050,
|
|
[0x1]: 0xa090,
|
|
[0x2]: 0xc0b0,
|
|
[0x3]: 0x2301,
|
|
[0x4]: 0x2301,
|
|
[0x5]: 0x2301,
|
|
[0x6]: 0x2301,
|
|
[0x7]: 0x2301,
|
|
[0x8]: 0x2301,
|
|
[0x9]: 0x2301,
|
|
[0xa]: 0x2301,
|
|
[0xb]: 0x2301,
|
|
[0xc]: 0x2301,
|
|
[0xd]: 0x2301,
|
|
[0xe]: 0x2301,
|
|
[0xf]: 0x2301,
|
|
],
|
|
},
|
|
],
|
|
},
|
|
small_slots: StatePart {
|
|
value: [
|
|
1,
|
|
0,
|
|
0,
|
|
1,
|
|
2,
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
2,
|
|
2,
|
|
0,
|
|
],
|
|
},
|
|
big_slots: StatePart {
|
|
value: [
|
|
2,
|
|
1,
|
|
0,
|
|
176,
|
|
-64,
|
|
2,
|
|
0,
|
|
0,
|
|
208,
|
|
-32,
|
|
1,
|
|
1,
|
|
2,
|
|
1,
|
|
0,
|
|
176,
|
|
-64,
|
|
2,
|
|
0,
|
|
0,
|
|
208,
|
|
-32,
|
|
1,
|
|
1,
|
|
208,
|
|
-32,
|
|
1,
|
|
1,
|
|
],
|
|
},
|
|
},
|
|
io: Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
},
|
|
main_module: SimulationModuleState {
|
|
base_targets: [
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.r,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.w,
|
|
],
|
|
uninitialized_ios: {},
|
|
io_targets: {
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.r,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.r.addr,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.r.clk,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.r.data,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.r.data.0,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.r.data.1,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.r.en,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.w,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.w.addr,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.w.clk,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.w.data,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.w.data.0,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.w.data.1,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.w.en,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.w.mask,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.w.mask.0,
|
|
Instance {
|
|
name: <simulator>::memories,
|
|
instantiated: Module {
|
|
name: memories,
|
|
..
|
|
},
|
|
}.w.mask.1,
|
|
},
|
|
did_initial_settle: true,
|
|
},
|
|
extern_modules: [],
|
|
state_ready_to_run: false,
|
|
trace_decls: TraceModule {
|
|
name: "memories",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "r",
|
|
child: TraceBundle {
|
|
name: "r",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(0),
|
|
name: "addr",
|
|
ty: UInt<4>,
|
|
flow: Source,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(1),
|
|
name: "en",
|
|
flow: Source,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(2),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
TraceBundle {
|
|
name: "data",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(3),
|
|
name: "0",
|
|
ty: UInt<8>,
|
|
flow: Sink,
|
|
},
|
|
TraceSInt {
|
|
location: TraceScalarId(4),
|
|
name: "1",
|
|
ty: SInt<8>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
},
|
|
flow: Source,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "w",
|
|
child: TraceBundle {
|
|
name: "w",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(5),
|
|
name: "addr",
|
|
ty: UInt<4>,
|
|
flow: Source,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(6),
|
|
name: "en",
|
|
flow: Source,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(7),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
TraceBundle {
|
|
name: "data",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(8),
|
|
name: "0",
|
|
ty: UInt<8>,
|
|
flow: Source,
|
|
},
|
|
TraceSInt {
|
|
location: TraceScalarId(9),
|
|
name: "1",
|
|
ty: SInt<8>,
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceBundle {
|
|
name: "mask",
|
|
fields: [
|
|
TraceBool {
|
|
location: TraceScalarId(10),
|
|
name: "0",
|
|
flow: Source,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(11),
|
|
name: "1",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
0: Bool,
|
|
/* offset = 1 */
|
|
1: Bool,
|
|
},
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
/* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
/* offset = 22 */
|
|
mask: Bundle {
|
|
/* offset = 0 */
|
|
0: Bool,
|
|
/* offset = 1 */
|
|
1: Bool,
|
|
},
|
|
},
|
|
flow: Source,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
/* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
/* offset = 22 */
|
|
mask: Bundle {
|
|
/* offset = 0 */
|
|
0: Bool,
|
|
/* offset = 1 */
|
|
1: Bool,
|
|
},
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceMem {
|
|
id: TraceMemoryId(0),
|
|
name: "mem",
|
|
stride: 16,
|
|
element_type: TraceBundle {
|
|
name: "mem",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 16,
|
|
stride: 16,
|
|
start: 0,
|
|
len: 8,
|
|
},
|
|
name: "0",
|
|
ty: UInt<8>,
|
|
flow: Duplex,
|
|
},
|
|
TraceSInt {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 16,
|
|
stride: 16,
|
|
start: 8,
|
|
len: 8,
|
|
},
|
|
name: "1",
|
|
ty: SInt<8>,
|
|
flow: Duplex,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
flow: Duplex,
|
|
},
|
|
ports: [
|
|
TraceMemPort {
|
|
name: "r0",
|
|
bundle: TraceBundle {
|
|
name: "r0",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(12),
|
|
name: "addr",
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(13),
|
|
name: "en",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(14),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceBundle {
|
|
name: "data",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(15),
|
|
name: "0",
|
|
ty: UInt<8>,
|
|
flow: Source,
|
|
},
|
|
TraceSInt {
|
|
location: TraceScalarId(16),
|
|
name: "1",
|
|
ty: SInt<8>,
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
},
|
|
},
|
|
TraceMemPort {
|
|
name: "w1",
|
|
bundle: TraceBundle {
|
|
name: "w1",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(17),
|
|
name: "addr",
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(18),
|
|
name: "en",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(19),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceBundle {
|
|
name: "data",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(20),
|
|
name: "0",
|
|
ty: UInt<8>,
|
|
flow: Sink,
|
|
},
|
|
TraceSInt {
|
|
location: TraceScalarId(21),
|
|
name: "1",
|
|
ty: SInt<8>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
TraceBundle {
|
|
name: "mask",
|
|
fields: [
|
|
TraceBool {
|
|
location: TraceScalarId(22),
|
|
name: "0",
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(23),
|
|
name: "1",
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
0: Bool,
|
|
/* offset = 1 */
|
|
1: Bool,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
/* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
/* offset = 22 */
|
|
mask: Bundle {
|
|
/* offset = 0 */
|
|
0: Bool,
|
|
/* offset = 1 */
|
|
1: Bool,
|
|
},
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
/* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
/* offset = 22 */
|
|
mask: Bundle {
|
|
/* offset = 0 */
|
|
0: Bool,
|
|
/* offset = 1 */
|
|
1: Bool,
|
|
},
|
|
},
|
|
},
|
|
],
|
|
array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
|
|
},
|
|
],
|
|
},
|
|
traces: [
|
|
SimTrace {
|
|
id: TraceScalarId(0),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(0),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(1),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(1),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(2),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(2),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(3),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(3),
|
|
ty: UInt<8>,
|
|
},
|
|
state: 0xb0,
|
|
last_state: 0xb0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(4),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(4),
|
|
ty: SInt<8>,
|
|
},
|
|
state: 0xc0,
|
|
last_state: 0xc0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(5),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(5),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(6),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(6),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(7),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(7),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(8),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(8),
|
|
ty: UInt<8>,
|
|
},
|
|
state: 0xd0,
|
|
last_state: 0xd0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(9),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(9),
|
|
ty: SInt<8>,
|
|
},
|
|
state: 0xe0,
|
|
last_state: 0xe0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(10),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(10),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(11),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(11),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(12),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(12),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(13),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(13),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(14),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(14),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(15),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(15),
|
|
ty: UInt<8>,
|
|
},
|
|
state: 0xb0,
|
|
last_state: 0xb0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(16),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(16),
|
|
ty: SInt<8>,
|
|
},
|
|
state: 0xc0,
|
|
last_state: 0xc0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(17),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(17),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(18),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(18),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(19),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(19),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(20),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(20),
|
|
ty: UInt<8>,
|
|
},
|
|
state: 0xd0,
|
|
last_state: 0xd0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(21),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(21),
|
|
ty: SInt<8>,
|
|
},
|
|
state: 0xe0,
|
|
last_state: 0xe0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(22),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(22),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(23),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(23),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
],
|
|
trace_memories: {
|
|
StatePartIndex<Memories>(0): TraceMem {
|
|
id: TraceMemoryId(0),
|
|
name: "mem",
|
|
stride: 16,
|
|
element_type: TraceBundle {
|
|
name: "mem",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 16,
|
|
stride: 16,
|
|
start: 0,
|
|
len: 8,
|
|
},
|
|
name: "0",
|
|
ty: UInt<8>,
|
|
flow: Duplex,
|
|
},
|
|
TraceSInt {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 16,
|
|
stride: 16,
|
|
start: 8,
|
|
len: 8,
|
|
},
|
|
name: "1",
|
|
ty: SInt<8>,
|
|
flow: Duplex,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
flow: Duplex,
|
|
},
|
|
ports: [
|
|
TraceMemPort {
|
|
name: "r0",
|
|
bundle: TraceBundle {
|
|
name: "r0",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(12),
|
|
name: "addr",
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(13),
|
|
name: "en",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(14),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceBundle {
|
|
name: "data",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(15),
|
|
name: "0",
|
|
ty: UInt<8>,
|
|
flow: Source,
|
|
},
|
|
TraceSInt {
|
|
location: TraceScalarId(16),
|
|
name: "1",
|
|
ty: SInt<8>,
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
},
|
|
},
|
|
TraceMemPort {
|
|
name: "w1",
|
|
bundle: TraceBundle {
|
|
name: "w1",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(17),
|
|
name: "addr",
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(18),
|
|
name: "en",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(19),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceBundle {
|
|
name: "data",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(20),
|
|
name: "0",
|
|
ty: UInt<8>,
|
|
flow: Sink,
|
|
},
|
|
TraceSInt {
|
|
location: TraceScalarId(21),
|
|
name: "1",
|
|
ty: SInt<8>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
TraceBundle {
|
|
name: "mask",
|
|
fields: [
|
|
TraceBool {
|
|
location: TraceScalarId(22),
|
|
name: "0",
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(23),
|
|
name: "1",
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
0: Bool,
|
|
/* offset = 1 */
|
|
1: Bool,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
/* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
/* offset = 22 */
|
|
mask: Bundle {
|
|
/* offset = 0 */
|
|
0: Bool,
|
|
/* offset = 1 */
|
|
1: Bool,
|
|
},
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<4>,
|
|
/* offset = 4 */
|
|
en: Bool,
|
|
/* offset = 5 */
|
|
clk: Clock,
|
|
/* offset = 6 */
|
|
data: Bundle {
|
|
/* offset = 0 */
|
|
0: UInt<8>,
|
|
/* offset = 8 */
|
|
1: SInt<8>,
|
|
},
|
|
/* offset = 22 */
|
|
mask: Bundle {
|
|
/* offset = 0 */
|
|
0: Bool,
|
|
/* offset = 1 */
|
|
1: Bool,
|
|
},
|
|
},
|
|
},
|
|
],
|
|
array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
|
|
},
|
|
},
|
|
trace_writers: [
|
|
Running(
|
|
VcdWriter {
|
|
finished_init: true,
|
|
timescale: 1 ps,
|
|
..
|
|
},
|
|
),
|
|
],
|
|
instant: 22 μs,
|
|
clocks_triggered: [
|
|
StatePartIndex<SmallSlots>(1),
|
|
StatePartIndex<SmallSlots>(6),
|
|
],
|
|
..
|
|
} |