fayalite/crates/fayalite/tests/sim/expected/memories2.vcd
Jacob Lifshay c756aeec70
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tests/sim: add test for memory rw port
2024-12-12 20:50:41 -08:00

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$timescale 1 ps $end
$scope module memories2 $end
$scope struct rw $end
$var wire 3 ! addr $end
$var wire 1 " en $end
$var wire 1 # clk $end
$var wire 2 $ rdata $end
$var wire 1 % wmode $end
$var wire 2 & wdata $end
$var wire 1 ' wmask $end
$upscope $end
$scope struct mem $end
$scope struct contents $end
$scope struct [0] $end
$scope struct mem $end
$var string 1 1 \$tag $end
$var reg 1 6 HdlSome $end
$upscope $end
$upscope $end
$scope struct [1] $end
$scope struct mem $end
$var string 1 2 \$tag $end
$var reg 1 7 HdlSome $end
$upscope $end
$upscope $end
$scope struct [2] $end
$scope struct mem $end
$var string 1 3 \$tag $end
$var reg 1 8 HdlSome $end
$upscope $end
$upscope $end
$scope struct [3] $end
$scope struct mem $end
$var string 1 4 \$tag $end
$var reg 1 9 HdlSome $end
$upscope $end
$upscope $end
$scope struct [4] $end
$scope struct mem $end
$var string 1 5 \$tag $end
$var reg 1 : HdlSome $end
$upscope $end
$upscope $end
$upscope $end
$scope struct rw0 $end
$var wire 3 ( addr $end
$var wire 1 ) en $end
$var wire 1 * clk $end
$scope struct rdata $end
$var string 1 + \$tag $end
$var wire 1 , HdlSome $end
$upscope $end
$var wire 1 - wmode $end
$scope struct wdata $end
$var string 1 . \$tag $end
$var wire 1 / HdlSome $end
$upscope $end
$var wire 1 0 wmask $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
sHdlSome\x20(1) 1
16
sHdlSome\x20(1) 2
17
sHdlSome\x20(1) 3
18
sHdlSome\x20(1) 4
19
sHdlSome\x20(1) 5
1:
b0 !
0"
0#
b0 $
0%
b0 &
0'
b0 (
0)
0*
sHdlNone\x20(0) +
0,
0-
sHdlNone\x20(0) .
0/
00
$end
#250000
1#
1*
#500000
#750000
0#
0*
#1000000
1"
1)
#1250000
1#
1*
b11 $
sHdlSome\x20(1) +
1,
#1500000
#1750000
0#
0*
#2000000
0"
0)
#2250000
1#
1*
b0 $
sHdlNone\x20(0) +
0,
#2500000
#2750000
0#
0*
#3000000
1"
1%
1'
1)
1-
10
#3250000
sHdlNone\x20(0) 1
06
1#
1*
#3500000
#3750000
0#
0*
#4000000
0%
0'
0-
00
#4250000
1#
1*
#4500000
#4750000
0#
0*
#5000000
1%
b11 &
1-
sHdlSome\x20(1) .
1/
#5250000
1#
1*
#5500000
#5750000
0#
0*
#6000000
b1 !
b1 &
1'
b1 (
0/
10
#6250000
sHdlSome\x20(1) 2
07
1#
1*
#6500000
#6750000
0#
0*
#7000000
b10 !
b10 &
b10 (
sHdlNone\x20(0) .
#7250000
sHdlNone\x20(0) 3
08
1#
1*
#7500000
#7750000
0#
0*
#8000000
b11 !
b11 &
b11 (
sHdlSome\x20(1) .
1/
#8250000
sHdlSome\x20(1) 4
19
1#
1*
#8500000
#8750000
0#
0*
#9000000
b100 !
b10 &
b100 (
sHdlNone\x20(0) .
0/
#9250000
sHdlNone\x20(0) 5
0:
1#
1*
#9500000
#9750000
0#
0*
#10000000
b101 !
b1 &
b101 (
sHdlSome\x20(1) .
#10250000
1#
1*
#10500000
#10750000
0#
0*
#11000000
b110 !
b110 (
#11250000
1#
1*
#11500000
#11750000
0#
0*
#12000000
b111 !
b111 (
#12250000
1#
1*
#12500000
#12750000
0#
0*
#13000000
0%
b0 &
0'
0-
sHdlNone\x20(0) .
00
#13250000
1#
1*
#13500000
#13750000
0#
0*
#14000000
b110 !
b110 (
#14250000
1#
1*
#14500000
#14750000
0#
0*
#15000000
b101 !
b101 (
#15250000
1#
1*
#15500000
#15750000
0#
0*
#16000000
b100 !
b100 (
#16250000
1#
1*
#16500000
#16750000
0#
0*
#17000000
b11 !
b11 (
#17250000
1#
1*
b11 $
sHdlSome\x20(1) +
1,
#17500000
#17750000
0#
0*
#18000000
b10 !
b10 (
#18250000
1#
1*
b0 $
sHdlNone\x20(0) +
0,
#18500000
#18750000
0#
0*
#19000000
b0 !
b0 (
#19250000
1#
1*
#19500000
#19750000
0#
0*
#20000000
b1 !
b1 (
#20250000
1#
1*
b1 $
sHdlSome\x20(1) +
#20500000
#20750000
0#
0*
#21000000
b0 !
0"
b0 (
0)
#21250000
1#
1*
b0 $
sHdlNone\x20(0) +
#21500000
#21750000
0#
0*
#22000000