523 lines
No EOL
17 KiB
Text
523 lines
No EOL
17 KiB
Text
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 6,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[0]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[1]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[2]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[0]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[1]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[2]",
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ty: UInt<8>,
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},
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],
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..
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},
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sim_only_slots: StatePartLayout<SimOnlySlots> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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0: Return,
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],
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..
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},
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pc: 0,
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memory_write_log: [],
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memories: StatePart {
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value: [],
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},
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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0,
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0,
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0,
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49,
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50,
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50,
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],
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},
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sim_only_slots: StatePart {
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value: [],
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},
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},
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io: Instance {
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name: <simulator>::sim_fork_join,
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instantiated: Module {
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name: sim_fork_join,
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..
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},
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},
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main_module: SimulationModuleState {
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base_targets: [
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Instance {
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name: <simulator>::sim_fork_join,
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instantiated: Module {
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name: sim_fork_join,
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..
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},
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}.clocks,
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Instance {
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name: <simulator>::sim_fork_join,
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instantiated: Module {
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name: sim_fork_join,
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..
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},
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}.outputs,
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],
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uninitialized_ios: {},
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io_targets: {
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Instance {
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name: <simulator>::sim_fork_join,
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instantiated: Module {
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name: sim_fork_join,
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..
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},
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}.clocks,
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Instance {
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name: <simulator>::sim_fork_join,
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instantiated: Module {
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name: sim_fork_join,
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..
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},
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}.clocks[0],
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Instance {
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name: <simulator>::sim_fork_join,
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instantiated: Module {
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name: sim_fork_join,
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..
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},
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}.clocks[1],
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Instance {
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name: <simulator>::sim_fork_join,
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instantiated: Module {
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name: sim_fork_join,
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..
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},
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}.clocks[2],
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Instance {
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name: <simulator>::sim_fork_join,
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instantiated: Module {
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name: sim_fork_join,
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..
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},
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}.outputs,
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Instance {
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name: <simulator>::sim_fork_join,
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instantiated: Module {
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name: sim_fork_join,
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..
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},
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}.outputs[0],
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Instance {
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name: <simulator>::sim_fork_join,
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instantiated: Module {
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name: sim_fork_join,
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..
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},
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}.outputs[1],
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Instance {
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name: <simulator>::sim_fork_join,
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instantiated: Module {
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name: sim_fork_join,
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..
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},
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}.outputs[2],
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},
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did_initial_settle: true,
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},
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extern_modules: [
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SimulationExternModuleState {
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module_state: SimulationModuleState {
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base_targets: [
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ModuleIO {
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name: sim_fork_join::clocks,
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is_input: true,
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ty: Array<Clock, 3>,
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..
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},
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ModuleIO {
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name: sim_fork_join::outputs,
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is_input: false,
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ty: Array<UInt<8>, 3>,
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..
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},
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],
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uninitialized_ios: {},
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io_targets: {
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ModuleIO {
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name: sim_fork_join::clocks,
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is_input: true,
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ty: Array<Clock, 3>,
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..
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},
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ModuleIO {
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name: sim_fork_join::clocks,
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is_input: true,
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ty: Array<Clock, 3>,
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..
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}[0],
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ModuleIO {
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name: sim_fork_join::clocks,
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is_input: true,
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ty: Array<Clock, 3>,
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..
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}[1],
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ModuleIO {
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name: sim_fork_join::clocks,
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is_input: true,
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ty: Array<Clock, 3>,
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..
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}[2],
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ModuleIO {
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name: sim_fork_join::outputs,
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is_input: false,
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ty: Array<UInt<8>, 3>,
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..
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},
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ModuleIO {
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name: sim_fork_join::outputs,
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is_input: false,
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ty: Array<UInt<8>, 3>,
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..
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}[0],
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ModuleIO {
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name: sim_fork_join::outputs,
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is_input: false,
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ty: Array<UInt<8>, 3>,
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..
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}[1],
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ModuleIO {
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name: sim_fork_join::outputs,
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is_input: false,
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ty: Array<UInt<8>, 3>,
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..
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}[2],
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},
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did_initial_settle: true,
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},
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sim: ExternModuleSimulation {
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generator: SimGeneratorFn {
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args: (
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ModuleIO {
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name: sim_fork_join::clocks,
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is_input: true,
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ty: Array<Clock, 3>,
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..
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},
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ModuleIO {
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name: sim_fork_join::outputs,
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is_input: false,
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ty: Array<UInt<8>, 3>,
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..
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},
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),
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f: ...,
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},
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sim_io_to_generator_map: {
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ModuleIO {
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name: sim_fork_join::clocks,
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is_input: true,
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ty: Array<Clock, 3>,
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..
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}: ModuleIO {
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name: sim_fork_join::clocks,
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is_input: true,
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ty: Array<Clock, 3>,
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..
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},
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ModuleIO {
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name: sim_fork_join::outputs,
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is_input: false,
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ty: Array<UInt<8>, 3>,
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..
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}: ModuleIO {
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name: sim_fork_join::outputs,
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is_input: false,
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ty: Array<UInt<8>, 3>,
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..
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},
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},
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source_location: SourceLocation(
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module-XXXXXXXXXX.rs:4:1,
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),
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},
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running_generator: Some(
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...,
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),
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},
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],
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trace_decls: TraceModule {
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name: "sim_fork_join",
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children: [
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TraceModuleIO {
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name: "clocks",
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child: TraceArray {
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name: "clocks",
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elements: [
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TraceClock {
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location: TraceScalarId(0),
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name: "[0]",
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flow: Source,
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},
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TraceClock {
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location: TraceScalarId(1),
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name: "[1]",
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flow: Source,
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},
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TraceClock {
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location: TraceScalarId(2),
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name: "[2]",
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flow: Source,
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},
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],
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ty: Array<Clock, 3>,
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flow: Source,
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},
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ty: Array<Clock, 3>,
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flow: Source,
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},
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TraceModuleIO {
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name: "outputs",
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child: TraceArray {
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name: "outputs",
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elements: [
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TraceUInt {
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location: TraceScalarId(3),
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name: "[0]",
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ty: UInt<8>,
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flow: Sink,
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},
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TraceUInt {
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location: TraceScalarId(4),
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name: "[1]",
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ty: UInt<8>,
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flow: Sink,
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},
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TraceUInt {
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location: TraceScalarId(5),
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name: "[2]",
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ty: UInt<8>,
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flow: Sink,
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},
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],
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ty: Array<UInt<8>, 3>,
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flow: Sink,
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},
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ty: Array<UInt<8>, 3>,
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flow: Sink,
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},
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],
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},
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traces: [
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SimTrace {
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id: TraceScalarId(0),
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kind: BigClock {
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index: StatePartIndex<BigSlots>(0),
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},
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state: 0x0,
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last_state: 0x0,
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},
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SimTrace {
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id: TraceScalarId(1),
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kind: BigClock {
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index: StatePartIndex<BigSlots>(1),
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},
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state: 0x0,
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last_state: 0x0,
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},
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SimTrace {
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id: TraceScalarId(2),
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kind: BigClock {
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index: StatePartIndex<BigSlots>(2),
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},
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state: 0x0,
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last_state: 0x1,
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},
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SimTrace {
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id: TraceScalarId(3),
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kind: BigUInt {
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index: StatePartIndex<BigSlots>(3),
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ty: UInt<8>,
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},
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state: 0x31,
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last_state: 0x31,
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},
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SimTrace {
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id: TraceScalarId(4),
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kind: BigUInt {
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index: StatePartIndex<BigSlots>(4),
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ty: UInt<8>,
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},
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state: 0x32,
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last_state: 0x32,
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},
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SimTrace {
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id: TraceScalarId(5),
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kind: BigUInt {
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index: StatePartIndex<BigSlots>(5),
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ty: UInt<8>,
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},
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state: 0x32,
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last_state: 0x32,
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},
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],
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trace_memories: {},
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trace_writers: [
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Running(
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VcdWriter {
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finished_init: true,
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timescale: 1 ps,
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..
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},
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),
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],
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clocks_triggered: [],
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event_queue: EventQueue(EventQueueData {
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instant: 648 μs,
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events: {},
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}),
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waiting_sensitivity_sets_by_address: {
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SensitivitySet {
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id: 198,
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values: {
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CompiledValue {
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layout: CompiledTypeLayout {
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ty: Clock,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Clock,
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},
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],
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..
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},
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sim_only_slots: StatePartLayout<SimOnlySlots> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
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},
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write: None,
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}: SimValue {
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ty: Clock,
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value: OpaqueSimValue {
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bits: 0x0_u1,
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sim_only_values: [],
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},
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},
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},
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changed: Cell {
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value: false,
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},
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..
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},
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},
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waiting_sensitivity_sets_by_compiled_value: {
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CompiledValue {
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layout: CompiledTypeLayout {
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ty: Clock,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Clock,
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},
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],
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..
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},
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sim_only_slots: StatePartLayout<SimOnlySlots> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
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},
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write: None,
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}: (
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SimValue {
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ty: Clock,
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value: OpaqueSimValue {
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bits: 0x0_u1,
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sim_only_values: [],
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},
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},
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{
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SensitivitySet {
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id: 198,
|
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..
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},
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},
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),
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},
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..
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} |