681 lines
27 KiB
Plaintext
681 lines
27 KiB
Plaintext
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 4,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 13,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
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ty: SyncReset,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next",
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ty: Bool,
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},
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],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:13:1
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0: Copy {
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dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
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src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:12:1
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1: Copy {
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dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
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src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:10:1
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2: Copy {
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dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
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src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:8:1
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3: Copy {
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dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
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src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:6:1
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4: Copy {
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dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
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src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:5:1
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5: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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6: Const {
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dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
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value: 0,
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},
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// at: module-XXXXXXXXXX.rs:5:1
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7: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
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},
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8: AndSmall {
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dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
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rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
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},
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9: BranchIfSmallZero {
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target: 14,
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value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
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},
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10: BranchIfSmallNonZero {
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target: 13,
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value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
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},
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11: Copy {
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dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
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src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
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},
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12: Branch {
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target: 14,
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},
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13: Copy {
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dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
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src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:7:1
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14: BranchIfSmallZero {
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target: 19,
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value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
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},
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15: BranchIfSmallNonZero {
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target: 18,
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value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
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},
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16: Copy {
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dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
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src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
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},
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17: Branch {
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target: 19,
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},
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18: Copy {
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dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
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src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:9:1
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19: BranchIfSmallZero {
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target: 24,
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value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
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},
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20: BranchIfSmallNonZero {
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target: 23,
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value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
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},
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21: Copy {
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dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
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src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
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},
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22: Branch {
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target: 24,
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},
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23: Copy {
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dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
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src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:11:1
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24: BranchIfSmallZero {
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target: 29,
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value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
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},
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25: BranchIfSmallNonZero {
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target: 28,
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value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
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},
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26: Copy {
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dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
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src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
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},
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27: Branch {
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target: 29,
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},
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28: Copy {
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dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
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src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:5:1
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29: NotSmall {
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dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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30: Return,
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],
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..
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},
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pc: 30,
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memory_write_log: [],
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memories: StatePart {
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value: [],
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},
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small_slots: StatePart {
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value: [
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18446744073709551614,
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0,
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1,
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0,
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],
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},
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big_slots: StatePart {
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value: [
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1,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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],
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},
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},
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io: Instance {
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name: <simulator>::shift_register,
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instantiated: Module {
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name: shift_register,
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..
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},
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},
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uninitialized_inputs: {},
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io_targets: {
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Instance {
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name: <simulator>::shift_register,
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instantiated: Module {
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name: shift_register,
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..
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},
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}.cd: CompiledValue {
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layout: CompiledTypeLayout {
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ty: Bundle {
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/* offset = 0 */
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clk: Clock,
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/* offset = 1 */
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rst: SyncReset,
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},
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 2,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
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ty: SyncReset,
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},
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],
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..
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},
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},
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body: Bundle {
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fields: [
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CompiledBundleField {
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offset: TypeIndex {
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small_slots: StatePartIndex<SmallSlots>(0),
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big_slots: StatePartIndex<BigSlots>(0),
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},
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ty: CompiledTypeLayout {
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ty: Clock,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Clock,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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},
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CompiledBundleField {
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offset: TypeIndex {
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small_slots: StatePartIndex<SmallSlots>(0),
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big_slots: StatePartIndex<BigSlots>(1),
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},
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ty: CompiledTypeLayout {
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ty: SyncReset,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: SyncReset,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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},
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],
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},
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
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},
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write: None,
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},
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Instance {
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name: <simulator>::shift_register,
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instantiated: Module {
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name: shift_register,
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..
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},
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}.cd.clk: CompiledValue {
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layout: CompiledTypeLayout {
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ty: Clock,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
|
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Clock,
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},
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],
|
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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},
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write: None,
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},
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Instance {
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name: <simulator>::shift_register,
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instantiated: Module {
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name: shift_register,
|
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..
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},
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}.cd.rst: CompiledValue {
|
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layout: CompiledTypeLayout {
|
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ty: SyncReset,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
|
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debug_data: [],
|
|
..
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},
|
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big_slots: StatePartLayout<BigSlots> {
|
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len: 1,
|
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debug_data: [
|
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SlotDebugData {
|
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name: "",
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ty: SyncReset,
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},
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],
|
|
..
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},
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},
|
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body: Scalar,
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},
|
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
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},
|
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write: None,
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},
|
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Instance {
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name: <simulator>::shift_register,
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instantiated: Module {
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name: shift_register,
|
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..
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},
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}.d: CompiledValue {
|
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layout: CompiledTypeLayout {
|
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ty: Bool,
|
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layout: TypeLayout {
|
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small_slots: StatePartLayout<SmallSlots> {
|
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len: 0,
|
|
debug_data: [],
|
|
..
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},
|
|
big_slots: StatePartLayout<BigSlots> {
|
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len: 1,
|
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debug_data: [
|
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SlotDebugData {
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name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
|
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ty: Bool,
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},
|
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],
|
|
..
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},
|
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},
|
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body: Scalar,
|
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},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
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|
},
|
|
write: None,
|
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},
|
|
Instance {
|
|
name: <simulator>::shift_register,
|
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instantiated: Module {
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name: shift_register,
|
|
..
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|
},
|
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}.q: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
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ty: Bool,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
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|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
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name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
|
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ty: Bool,
|
|
},
|
|
],
|
|
..
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|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
},
|
|
made_initial_step: true,
|
|
needs_settle: false,
|
|
trace_decls: TraceModule {
|
|
name: "shift_register",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "cd",
|
|
child: TraceBundle {
|
|
name: "cd",
|
|
fields: [
|
|
TraceClock {
|
|
location: TraceScalarId(0),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
TraceSyncReset {
|
|
location: TraceScalarId(1),
|
|
name: "rst",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Source,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "d",
|
|
child: TraceBool {
|
|
location: TraceScalarId(2),
|
|
name: "d",
|
|
flow: Source,
|
|
},
|
|
ty: Bool,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "q",
|
|
child: TraceBool {
|
|
location: TraceScalarId(3),
|
|
name: "q",
|
|
flow: Sink,
|
|
},
|
|
ty: Bool,
|
|
flow: Sink,
|
|
},
|
|
TraceReg {
|
|
name: "reg0",
|
|
child: TraceBool {
|
|
location: TraceScalarId(4),
|
|
name: "reg0",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
TraceReg {
|
|
name: "reg1",
|
|
child: TraceBool {
|
|
location: TraceScalarId(5),
|
|
name: "reg1",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
TraceReg {
|
|
name: "reg2",
|
|
child: TraceBool {
|
|
location: TraceScalarId(6),
|
|
name: "reg2",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
TraceReg {
|
|
name: "reg3",
|
|
child: TraceBool {
|
|
location: TraceScalarId(7),
|
|
name: "reg3",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
],
|
|
},
|
|
traces: [
|
|
SimTrace {
|
|
id: TraceScalarId(0),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(0),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(1),
|
|
kind: BigSyncReset {
|
|
index: StatePartIndex<BigSlots>(1),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(2),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(2),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(3),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(3),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(4),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(4),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(5),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(7),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(6),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(9),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(7),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(11),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
],
|
|
trace_memories: {},
|
|
trace_writers: [
|
|
Running(
|
|
VcdWriter {
|
|
finished_init: true,
|
|
timescale: 1 ps,
|
|
..
|
|
},
|
|
),
|
|
],
|
|
instant: 66 μs,
|
|
clocks_triggered: [
|
|
StatePartIndex<SmallSlots>(1),
|
|
],
|
|
} |