fayalite

Jacob Lifshay 26224abe1c All checks were successful / test (pull_request) Successful in 4m8s Details / test (push) Successful in 4m42s Details sim: properly update all VCD wires when they share simulation state		2026-05-05 21:12:00 -07:00
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sim/expected	sim: properly update all VCD wires when they share simulation state	2026-05-05 21:12:00 -07:00
ui	add support for custom debug/display formatting of #[hdl] structs/enums	2026-04-30 23:10:49 -07:00
formal.rs	move FormalMode to crate::testing and add to prelude	2025-10-24 00:14:04 -07:00
hdl_types.rs	silence warning for enums with only one variant	2026-02-23 16:07:05 -08:00
hdl_types_fmt.rs	add support for custom debug/display formatting of #[hdl] structs/enums	2026-04-30 23:10:49 -07:00
module.rs	implement #[hdl(cmp_eq)] for enums	2026-05-01 18:34:49 -07:00
sim.rs	sim: properly update all VCD wires when they share simulation state	2026-05-05 21:12:00 -07:00
ui.rs	initial public commit	2024-06-10 23:09:13 -07:00