fayalite/crates/fayalite/tests/sim/expected/mod1.vcd
Jacob Lifshay 80b92c7dd3
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change vcd output to have module contents under instance's name, more closely matching how it works in verilog
2026-03-26 18:21:14 -07:00

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$timescale 1 ps $end
$scope module mod1 $end
$scope struct o $end
$var wire 4 avK(^ i $end
$var wire 2 Q2~aG o $end
$var wire 2 DXK'| i2 $end
$var wire 4 cPuix o2 $end
$upscope $end
$scope module child $end
$var wire 4 ($5K7 i $end
$var wire 2 %6Wv" o $end
$var wire 2 +|-AU i2 $end
$var wire 4 Hw?%j o2 $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
b11 avK(^
b11 Q2~aG
b10 DXK'|
b1110 cPuix
b11 ($5K7
b11 %6Wv"
b10 +|-AU
b1110 Hw?%j
$end
#1000000
b1010 avK(^
b10 Q2~aG
b1111 cPuix
b1010 ($5K7
b10 %6Wv"
b1111 Hw?%j
#2000000