crates/fayalite/tests/sim.rs

@@ -1276,3 +1276,134 @@ fn test_duplicate_names() {
         panic!();
     }
 }
+
+#[hdl_module(outline_generated)]
+pub fn array_rw() {
+    #[hdl]
+    let array_in: Array<UInt<8>, 16> = m.input();
+    #[hdl]
+    let array_out: Array<UInt<8>, 16> = m.output();
+    #[hdl]
+    let read_index: UInt<8> = m.input();
+    #[hdl]
+    let read_data: UInt<8> = m.output();
+    #[hdl]
+    let write_index: UInt<8> = m.input();
+    #[hdl]
+    let write_data: UInt<8> = m.input();
+    #[hdl]
+    let write_en: Bool = m.input();
+    #[hdl]
+    let array_wire = wire();
+    connect(array_wire, array_in);
+    connect(array_out, array_wire);
+    #[hdl]
+    if write_en {
+        connect(array_wire[write_index], write_data);
+    }
+    connect(read_data, array_wire[read_index]);
+}
+
+#[test]
+fn test_array_rw() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(array_rw());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    #[derive(Debug, PartialEq)]
+    struct State {
+        array_in: [u8; 16],
+        array_out: [u8; 16],
+        read_index: u8,
+        read_data: u8,
+        write_index: u8,
+        write_data: u8,
+        write_en: bool,
+    }
+    let mut states = Vec::new();
+    let array_in = [
+        0xFFu8, 0x7F, 0x3F, 0x1F, 0x0F, 0x07, 0x03, 0x01, //
+        0x00u8, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0xFE,
+    ];
+    for i in 0..=16 {
+        states.push(State {
+            array_in,
+            array_out: array_in,
+            read_index: i,
+            read_data: array_in.get(i as usize).copied().unwrap_or(0),
+            write_index: 0,
+            write_data: 0,
+            write_en: false,
+        });
+    }
+    for i in 0..=16u8 {
+        let mut array_out = array_in;
+        let write_data = i.wrapping_mul(i);
+        if let Some(v) = array_out.get_mut(i as usize) {
+            *v = write_data;
+        }
+        states.push(State {
+            array_in,
+            array_out,
+            read_index: 0,
+            read_data: array_out[0],
+            write_index: i,
+            write_data,
+            write_en: true,
+        });
+    }
+    for (cycle, expected) in states.into_iter().enumerate() {
+        let State {
+            array_in,
+            array_out: _,
+            read_index,
+            read_data: _,
+            write_index,
+            write_data,
+            write_en,
+        } = expected;
+        sim.write(sim.io().array_in, array_in);
+        sim.write(sim.io().read_index, read_index);
+        sim.write(sim.io().write_index, write_index);
+        sim.write(sim.io().write_data, write_data);
+        sim.write(sim.io().write_en, write_en);
+        sim.advance_time(SimDuration::from_micros(1));
+        let array_out = std::array::from_fn(|index| {
+            sim.read_bool_or_int(sim.io().array_out[index])
+                .to_bigint()
+                .try_into()
+                .expect("known to be in range")
+        });
+        let read_data = sim
+            .read_bool_or_int(sim.io().read_data)
+            .to_bigint()
+            .try_into()
+            .expect("known to be in range");
+        let state = State {
+            array_in,
+            array_out,
+            read_index,
+            read_data,
+            write_index,
+            write_data,
+            write_en,
+        };
+        assert_eq!(
+            state,
+            expected,
+            "vcd:\n{}\ncycle: {cycle}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/array_rw.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/array_rw.txt") {
+        panic!();
+    }
+}

crates/fayalite/tests/sim/expected/array_rw.vcd

@@ -0,0 +1,283 @@
+$timescale 1 ps $end
+$scope module array_rw $end
+$scope struct array_in $end
+$var wire 8 ! \[0] $end
+$var wire 8 " \[1] $end
+$var wire 8 # \[2] $end
+$var wire 8 $ \[3] $end
+$var wire 8 % \[4] $end
+$var wire 8 & \[5] $end
+$var wire 8 ' \[6] $end
+$var wire 8 ( \[7] $end
+$var wire 8 ) \[8] $end
+$var wire 8 * \[9] $end
+$var wire 8 + \[10] $end
+$var wire 8 , \[11] $end
+$var wire 8 - \[12] $end
+$var wire 8 . \[13] $end
+$var wire 8 / \[14] $end
+$var wire 8 0 \[15] $end
+$upscope $end
+$scope struct array_out $end
+$var wire 8 1 \[0] $end
+$var wire 8 2 \[1] $end
+$var wire 8 3 \[2] $end
+$var wire 8 4 \[3] $end
+$var wire 8 5 \[4] $end
+$var wire 8 6 \[5] $end
+$var wire 8 7 \[6] $end
+$var wire 8 8 \[7] $end
+$var wire 8 9 \[8] $end
+$var wire 8 : \[9] $end
+$var wire 8 ; \[10] $end
+$var wire 8 < \[11] $end
+$var wire 8 = \[12] $end
+$var wire 8 > \[13] $end
+$var wire 8 ? \[14] $end
+$var wire 8 @ \[15] $end
+$upscope $end
+$var wire 8 A read_index $end
+$var wire 8 B read_data $end
+$var wire 8 C write_index $end
+$var wire 8 D write_data $end
+$var wire 1 E write_en $end
+$scope struct array_wire $end
+$var wire 8 F \[0] $end
+$var wire 8 G \[1] $end
+$var wire 8 H \[2] $end
+$var wire 8 I \[3] $end
+$var wire 8 J \[4] $end
+$var wire 8 K \[5] $end
+$var wire 8 L \[6] $end
+$var wire 8 M \[7] $end
+$var wire 8 N \[8] $end
+$var wire 8 O \[9] $end
+$var wire 8 P \[10] $end
+$var wire 8 Q \[11] $end
+$var wire 8 R \[12] $end
+$var wire 8 S \[13] $end
+$var wire 8 T \[14] $end
+$var wire 8 U \[15] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b11111111 !
+b1111111 "
+b111111 #
+b11111 $
+b1111 %
+b111 &
+b11 '
+b1 (
+b0 )
+b10000000 *
+b11000000 +
+b11100000 ,
+b11110000 -
+b11111000 .
+b11111100 /
+b11111110 0
+b11111111 1
+b1111111 2
+b111111 3
+b11111 4
+b1111 5
+b111 6
+b11 7
+b1 8
+b0 9
+b10000000 :
+b11000000 ;
+b11100000 <
+b11110000 =
+b11111000 >
+b11111100 ?
+b11111110 @
+b0 A
+b11111111 B
+b0 C
+b0 D
+0E
+b11111111 F
+b1111111 G
+b111111 H
+b11111 I
+b1111 J
+b111 K
+b11 L
+b1 M
+b0 N
+b10000000 O
+b11000000 P
+b11100000 Q
+b11110000 R
+b11111000 S
+b11111100 T
+b11111110 U
+$end
+#1000000
+b1 A
+b1111111 B
+#2000000
+b10 A
+b111111 B
+#3000000
+b11 A
+b11111 B
+#4000000
+b100 A
+b1111 B
+#5000000
+b101 A
+b111 B
+#6000000
+b110 A
+b11 B
+#7000000
+b111 A
+b1 B
+#8000000
+b1000 A
+b0 B
+#9000000
+b1001 A
+b10000000 B
+#10000000
+b1010 A
+b11000000 B
+#11000000
+b1011 A
+b11100000 B
+#12000000
+b1100 A
+b11110000 B
+#13000000
+b1101 A
+b11111000 B
+#14000000
+b1110 A
+b11111100 B
+#15000000
+b1111 A
+b11111110 B
+#16000000
+b10000 A
+b0 B
+#17000000
+b0 1
+b0 A
+1E
+b0 F
+#18000000
+b11111111 1
+b1 2
+b11111111 B
+b1 C
+b1 D
+b11111111 F
+b1 G
+#19000000
+b1111111 2
+b100 3
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+b1111111 G
+b100 H
+#20000000
+b111111 3
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+b11 C
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+b1001 I
+#21000000
+b11111 4
+b10000 5
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+#22000000
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+#23000000
+b111 6
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+b111 K
+b100100 L
+#24000000
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+b110001 8
+b111 C
+b110001 D
+b11 L
+b110001 M
+#25000000
+b1 8
+b1000000 9
+b1000 C
+b1000000 D
+b1 M
+b1000000 N
+#26000000
+b0 9
+b1010001 :
+b1001 C
+b1010001 D
+b0 N
+b1010001 O
+#27000000
+b10000000 :
+b1100100 ;
+b1010 C
+b1100100 D
+b10000000 O
+b1100100 P
+#28000000
+b11000000 ;
+b1111001 <
+b1011 C
+b1111001 D
+b11000000 P
+b1111001 Q
+#29000000
+b11100000 <
+b10010000 =
+b1100 C
+b10010000 D
+b11100000 Q
+b10010000 R
+#30000000
+b11110000 =
+b10101001 >
+b1101 C
+b10101001 D
+b11110000 R
+b10101001 S
+#31000000
+b11111000 >
+b11000100 ?
+b1110 C
+b11000100 D
+b11111000 S
+b11000100 T
+#32000000
+b11111100 ?
+b11100001 @
+b1111 C
+b11100001 D
+b11111100 T
+b11100001 U
+#33000000
+b11111110 @
+b10000 C
+b0 D
+b11111110 U
+#34000000