.forgejo/workflows/deps.yml

@@ -19,7 +19,7 @@ jobs:
         id: restore-deps
         with:
           path: deps
-          key: ${{ github.repository }}-deps-${{ runner.os }}-${{ hashFiles('.forgejo/workflows/deps.yml') }}
+          key: deps-${{ runner.os }}-${{ hashFiles('.forgejo/workflows/deps.yml') }}
           lookup-only: true
       - name: Install Apt packages
         if: steps.restore-deps.outputs.cache-hit != 'true'

.forgejo/workflows/test.yml

@@ -38,7 +38,7 @@ jobs:
             z3 \
             zlib1g-dev
       - run: |
-          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.82.0
+          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.80.1
           source "$HOME/.cargo/env"
           echo "$PATH" >> "$GITHUB_PATH"
       - uses: https://code.forgejo.org/actions/cache/restore@v3
@@ -57,5 +57,4 @@ jobs:
           save-if: ${{ github.ref == 'refs/heads/master' }}
       - run: cargo test
       - run: cargo build --tests --features=unstable-doc
-      - run: cargo test --doc --features=unstable-doc
       - run: cargo doc --features=unstable-doc

Cargo.lock

@@ -301,7 +301,7 @@ checksum = "25cbce373ec4653f1a01a31e8a5e5ec0c622dc27ff9c4e6606eefef5cbbed4a5"
 
 [[package]]
 name = "fayalite"
-version = "0.3.0"
+version = "0.2.0"
 dependencies = [
  "bitvec",
  "blake3",
@@ -315,25 +315,23 @@ dependencies = [
  "num-bigint",
  "num-traits",
  "os_pipe",
- "petgraph",
  "serde",
  "serde_json",
  "tempfile",
  "trybuild",
- "vec_map",
  "which",
 ]
 
 [[package]]
 name = "fayalite-proc-macros"
-version = "0.3.0"
+version = "0.2.0"
 dependencies = [
  "fayalite-proc-macros-impl",
 ]
 
 [[package]]
 name = "fayalite-proc-macros-impl"
-version = "0.3.0"
+version = "0.2.0"
 dependencies = [
  "base16ct",
  "num-bigint",
@@ -347,7 +345,7 @@ dependencies = [
 
 [[package]]
 name = "fayalite-visit-gen"
-version = "0.3.0"
+version = "0.2.0"
 dependencies = [
  "indexmap",
  "prettyplease",
@@ -359,12 +357,6 @@ dependencies = [
  "thiserror",
 ]
 
-[[package]]
-name = "fixedbitset"
-version = "0.5.7"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1d674e81391d1e1ab681a28d99df07927c6d4aa5b027d7da16ba32d1d21ecd99"
-
 [[package]]
 name = "funty"
 version = "2.0.0"
@@ -431,9 +423,9 @@ checksum = "ce23b50ad8242c51a442f3ff322d56b02f08852c77e4c0b4d3fd684abc89c683"
 
 [[package]]
 name = "indexmap"
-version = "2.5.0"
+version = "2.2.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "68b900aa2f7301e21c36462b170ee99994de34dff39a4a6a528e80e7376d07e5"
+checksum = "168fb715dda47215e360912c096649d23d58bf392ac62f73919e831745e40f26"
 dependencies = [
  "equivalent",
  "hashbrown",
@@ -480,10 +472,11 @@ checksum = "01cda141df6706de531b6c46c3a33ecca755538219bd484262fa09410c13539c"
 
 [[package]]
 name = "num-bigint"
-version = "0.4.6"
+version = "0.4.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a5e44f723f1133c9deac646763579fdb3ac745e418f2a7af9cd0c431da1f20b9"
+checksum = "608e7659b5c3d7cba262d894801b9ec9d00de989e8a82bd4bef91d08da45cdc0"
 dependencies = [
+ "autocfg",
  "num-integer",
  "num-traits",
 ]
@@ -522,15 +515,6 @@ dependencies = [
  "windows-sys 0.59.0",
 ]
 
-[[package]]
-name = "petgraph"
-version = "0.6.5"
-source = "git+https://github.com/programmerjake/petgraph.git?rev=258ea8071209a924b73fe96f9f87a3b7b45cbc9f#258ea8071209a924b73fe96f9f87a3b7b45cbc9f"
-dependencies = [
- "fixedbitset",
- "indexmap",
-]
-
 [[package]]
 name = "prettyplease"
 version = "0.2.20"
@@ -543,9 +527,9 @@ dependencies = [
 
 [[package]]
 name = "proc-macro2"
-version = "1.0.92"
+version = "1.0.83"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "37d3544b3f2748c54e147655edb5025752e2303145b5aefb3c3ea2c78b973bb0"
+checksum = "0b33eb56c327dec362a9e55b3ad14f9d2f0904fb5a5b03b513ab5465399e9f43"
 dependencies = [
  "unicode-ident",
 ]
@@ -647,9 +631,9 @@ checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"
 
 [[package]]
 name = "syn"
-version = "2.0.93"
+version = "2.0.66"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9c786062daee0d6db1132800e623df74274a0a87322d8e183338e01b3d98d058"
+checksum = "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cdcff5"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -736,12 +720,6 @@ version = "0.2.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "06abde3611657adf66d383f00b093d7faecc7fa57071cce2578660c9f1010821"
 
-[[package]]
-name = "vec_map"
-version = "0.8.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f1bddf1187be692e79c5ffeab891132dfb0f236ed36a43c7ed39f1165ee20191"
-
 [[package]]
 name = "version_check"
 version = "0.9.4"

Cargo.toml

@@ -5,18 +5,18 @@ resolver = "2"
 members = ["crates/*"]
 
 [workspace.package]
-version = "0.3.0"
+version = "0.2.0"
 license = "LGPL-3.0-or-later"
 edition = "2021"
 repository = "https://git.libre-chip.org/libre-chip/fayalite"
 keywords = ["hdl", "hardware", "semiconductors", "firrtl", "fpga"]
 categories = ["simulation", "development-tools", "compilers"]
-rust-version = "1.82.0"
+rust-version = "1.80.1"
 
 [workspace.dependencies]
-fayalite-proc-macros = { version = "=0.3.0", path = "crates/fayalite-proc-macros" }
+fayalite-proc-macros = { version = "=0.2.0", path = "crates/fayalite-proc-macros" }
-fayalite-proc-macros-impl = { version = "=0.3.0", path = "crates/fayalite-proc-macros-impl" }
+fayalite-proc-macros-impl = { version = "=0.2.0", path = "crates/fayalite-proc-macros-impl" }
-fayalite-visit-gen = { version = "=0.3.0", path = "crates/fayalite-visit-gen" }
+fayalite-visit-gen = { version = "=0.2.0", path = "crates/fayalite-visit-gen" }
 base16ct = "0.2.0"
 bitvec = { version = "1.0.1", features = ["serde"] }
 blake3 = { version = "1.5.4", features = ["serde"] }
@@ -24,22 +24,19 @@ clap = { version = "4.5.9", features = ["derive", "env", "string"] }
 ctor = "0.2.8"
 eyre = "0.6.12"
 hashbrown = "0.14.3"
-indexmap = { version = "2.5.0", features = ["serde"] }
+indexmap = { version = "2.2.6", features = ["serde"] }
 jobslot = "0.2.19"
-num-bigint = "0.4.6"
+num-bigint = "0.4.4"
 num-traits = "0.2.16"
 os_pipe = "1.2.1"
-# TODO: switch back to crates.io once petgraph accepts PR #684 and releases a new version
-petgraph = { git = "https://github.com/programmerjake/petgraph.git", rev = "258ea8071209a924b73fe96f9f87a3b7b45cbc9f" }
 prettyplease = "0.2.20"
 proc-macro2 = "1.0.83"
 quote = "1.0.36"
 serde = { version = "1.0.202", features = ["derive"] }
 serde_json = { version = "1.0.117", features = ["preserve_order"] }
 sha2 = "0.10.8"
-syn = { version = "2.0.93", features = ["full", "fold", "visit", "extra-traits"] }
+syn = { version = "2.0.66", features = ["full", "fold", "visit", "extra-traits"] }
 tempfile = "3.10.1"
 thiserror = "1.0.61"
 trybuild = "1.0"
-vec_map = "0.8.2"
 which = "6.0.1"

crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs

@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: LGPL-3.0-or-later
-// See Notices.txt for copyright information
-use crate::{
-    hdl_type_common::{
-        get_target, ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType,
-        TypesParser,
-    },
-    kw, Errors, HdlAttr,
-};
-use proc_macro2::TokenStream;
-use quote::ToTokens;
-use syn::{parse_quote_spanned, Attribute, Generics, Ident, ItemType, Token, Type, Visibility};
-
-#[derive(Clone, Debug)]
-pub(crate) struct ParsedTypeAlias {
-    pub(crate) attrs: Vec<Attribute>,
-    pub(crate) options: HdlAttr<ItemOptions, kw::hdl>,
-    pub(crate) vis: Visibility,
-    pub(crate) type_token: Token![type],
-    pub(crate) ident: Ident,
-    pub(crate) generics: MaybeParsed<ParsedGenerics, Generics>,
-    pub(crate) eq_token: Token![=],
-    pub(crate) ty: MaybeParsed<ParsedType, Type>,
-    pub(crate) semi_token: Token![;],
-}
-
-impl ParsedTypeAlias {
-    fn parse(item: ItemType) -> syn::Result<Self> {
-        let ItemType {
-            mut attrs,
-            vis,
-            type_token,
-            ident,
-            mut generics,
-            eq_token,
-            ty,
-            semi_token,
-        } = item;
-        let mut errors = Errors::new();
-        let mut options = errors
-            .unwrap_or_default(HdlAttr::<ItemOptions, kw::hdl>::parse_and_take_attr(
-                &mut attrs,
-            ))
-            .unwrap_or_default();
-        errors.ok(options.body.validate());
-        let ItemOptions {
-            outline_generated: _,
-            target: _,
-            custom_bounds,
-            no_static,
-            no_runtime_generics: _,
-        } = options.body;
-        if let Some((no_static,)) = no_static {
-            errors.error(no_static, "no_static is not valid on type aliases");
-        }
-        let generics = if custom_bounds.is_some() {
-            MaybeParsed::Unrecognized(generics)
-        } else if let Some(generics) = errors.ok(ParsedGenerics::parse(&mut generics)) {
-            MaybeParsed::Parsed(generics)
-        } else {
-            MaybeParsed::Unrecognized(generics)
-        };
-        let ty = TypesParser::maybe_run(generics.as_ref(), *ty, &mut errors);
-        errors.finish()?;
-        Ok(Self {
-            attrs,
-            options,
-            vis,
-            type_token,
-            ident,
-            generics,
-            eq_token,
-            ty,
-            semi_token,
-        })
-    }
-}
-
-impl ToTokens for ParsedTypeAlias {
-    fn to_tokens(&self, tokens: &mut TokenStream) {
-        let Self {
-            attrs,
-            options,
-            vis,
-            type_token,
-            ident,
-            generics,
-            eq_token,
-            ty,
-            semi_token,
-        } = self;
-        let ItemOptions {
-            outline_generated: _,
-            target,
-            custom_bounds: _,
-            no_static: _,
-            no_runtime_generics,
-        } = &options.body;
-        let target = get_target(target, ident);
-        let mut type_attrs = attrs.clone();
-        type_attrs.push(parse_quote_spanned! {ident.span()=>
-            #[allow(type_alias_bounds)]
-        });
-        ItemType {
-            attrs: type_attrs,
-            vis: vis.clone(),
-            type_token: *type_token,
-            ident: ident.clone(),
-            generics: generics.into(),
-            eq_token: *eq_token,
-            ty: Box::new(ty.clone().into()),
-            semi_token: *semi_token,
-        }
-        .to_tokens(tokens);
-        if let (MaybeParsed::Parsed(generics), MaybeParsed::Parsed(ty), None) =
-            (generics, ty, no_runtime_generics)
-        {
-            generics.make_runtime_generics(tokens, vis, ident, &target, |context| {
-                ty.make_hdl_type_expr(context)
-            })
-        }
-    }
-}
-
-pub(crate) fn hdl_type_alias_impl(item: ItemType) -> syn::Result<TokenStream> {
-    let item = ParsedTypeAlias::parse(item)?;
-    let outline_generated = item.options.body.outline_generated;
-    let mut contents = item.to_token_stream();
-    if outline_generated.is_some() {
-        contents = crate::outline_generated(contents, "hdl-type-alias-");
-    }
-    Ok(contents)
-}

crates/fayalite-proc-macros-impl/src/hdl_type_common.rs

@@ -2044,7 +2044,6 @@ pub(crate) mod known_items {
     impl_known_item!(::fayalite::int::Size);
     impl_known_item!(::fayalite::int::UInt);
     impl_known_item!(::fayalite::int::UIntType);
-    impl_known_item!(::fayalite::reset::ResetType);
     impl_known_item!(::fayalite::ty::CanonicalType);
     impl_known_item!(::fayalite::ty::StaticType);
     impl_known_item!(::fayalite::ty::Type);
@@ -2240,7 +2239,6 @@ impl_bounds! {
         EnumType,
         IntType,
         KnownSize,
-        ResetType,
         Size,
         StaticType,
         Type,
@@ -2254,7 +2252,6 @@ impl_bounds! {
         BundleType,
         EnumType,
         IntType,
-        ResetType,
         StaticType,
         Type,
     }
@@ -2267,7 +2264,6 @@ impl From<ParsedTypeBound> for ParsedBound {
             ParsedTypeBound::BundleType(v) => ParsedBound::BundleType(v),
             ParsedTypeBound::EnumType(v) => ParsedBound::EnumType(v),
             ParsedTypeBound::IntType(v) => ParsedBound::IntType(v),
-            ParsedTypeBound::ResetType(v) => ParsedBound::ResetType(v),
             ParsedTypeBound::StaticType(v) => ParsedBound::StaticType(v),
             ParsedTypeBound::Type(v) => ParsedBound::Type(v),
         }
@@ -2281,7 +2277,6 @@ impl From<ParsedTypeBounds> for ParsedBounds {
             BundleType,
             EnumType,
             IntType,
-            ResetType,
             StaticType,
             Type,
         } = value;
@@ -2291,7 +2286,6 @@ impl From<ParsedTypeBounds> for ParsedBounds {
             EnumType,
             IntType,
             KnownSize: None,
-            ResetType,
             Size: None,
             StaticType,
             Type,
@@ -2320,11 +2314,6 @@ impl ParsedTypeBound {
                 ParsedTypeBound::BoolOrIntType(known_items::BoolOrIntType(span)),
                 ParsedTypeBound::Type(known_items::Type(span)),
             ]),
-            Self::ResetType(v) => ParsedTypeBounds::from_iter([
-                ParsedTypeBound::from(v),
-                ParsedTypeBound::StaticType(known_items::StaticType(span)),
-                ParsedTypeBound::Type(known_items::Type(span)),
-            ]),
             Self::StaticType(v) => ParsedTypeBounds::from_iter([
                 ParsedTypeBound::from(v),
                 ParsedTypeBound::Type(known_items::Type(span)),
@@ -2360,7 +2349,6 @@ impl From<ParsedSizeTypeBounds> for ParsedBounds {
             EnumType: None,
             IntType: None,
             KnownSize,
-            ResetType: None,
             Size,
             StaticType: None,
             Type: None,
@@ -2437,7 +2425,6 @@ impl ParsedBound {
             Self::EnumType(v) => ParsedBoundCategory::Type(ParsedTypeBound::EnumType(v)),
             Self::IntType(v) => ParsedBoundCategory::Type(ParsedTypeBound::IntType(v)),
             Self::KnownSize(v) => ParsedBoundCategory::SizeType(ParsedSizeTypeBound::KnownSize(v)),
-            Self::ResetType(v) => ParsedBoundCategory::Type(ParsedTypeBound::ResetType(v)),
             Self::Size(v) => ParsedBoundCategory::SizeType(ParsedSizeTypeBound::Size(v)),
             Self::StaticType(v) => ParsedBoundCategory::Type(ParsedTypeBound::StaticType(v)),
             Self::Type(v) => ParsedBoundCategory::Type(ParsedTypeBound::Type(v)),
@@ -3323,8 +3310,7 @@ impl ParsedGenerics {
                                 ParsedTypeBound::BoolOrIntType(_)
                                 | ParsedTypeBound::BundleType(_)
                                 | ParsedTypeBound::EnumType(_)
-                                | ParsedTypeBound::IntType(_)
+                                | ParsedTypeBound::IntType(_) => {
-                                | ParsedTypeBound::ResetType(_) => {
                                     errors.error(bound, "bound on mask type not implemented");
                                 }
                                 ParsedTypeBound::StaticType(bound) => {
@@ -4177,13 +4163,7 @@ impl MakeHdlTypeExpr for ParsedExpr {
         match self {
             ParsedExpr::Delimited(expr) => expr.make_hdl_type_expr(context),
             ParsedExpr::NamedParamConst(expr) => expr.make_hdl_type_expr(context),
-            ParsedExpr::Other(expr) => {
+            ParsedExpr::Other(expr) => (**expr).clone(),
-                let span = expr.span();
-                let const_usize = known_items::ConstUsize(span);
-                parse_quote_spanned! {expr.span()=>
-                    #const_usize::<{ #expr }>
-                }
-            }
         }
     }
 }

crates/fayalite-proc-macros-impl/src/lib.rs

@@ -3,29 +3,21 @@
 #![cfg_attr(test, recursion_limit = "512")]
 use proc_macro2::{Span, TokenStream};
 use quote::{quote, ToTokens};
-use std::{
+use std::io::{ErrorKind, Write};
-    collections::{hash_map::Entry, HashMap},
-    io::{ErrorKind, Write},
-};
 use syn::{
-    bracketed,
+    bracketed, parenthesized,
-    ext::IdentExt,
-    parenthesized,
     parse::{Parse, ParseStream, Parser},
     parse_quote,
-    punctuated::{Pair, Punctuated},
+    punctuated::Pair,
     spanned::Spanned,
-    token::{Bracket, Paren},
+    AttrStyle, Attribute, Error, Item, ItemFn, Token,
-    AttrStyle, Attribute, Error, Ident, Item, ItemFn, LitBool, LitStr, Meta, Token,
 };
 
 mod fold;
 mod hdl_bundle;
 mod hdl_enum;
-mod hdl_type_alias;
 mod hdl_type_common;
 mod module;
-mod process_cfg;
 
 pub(crate) trait CustomToken:
     Copy
@@ -66,11 +58,6 @@ mod kw {
         };
     }
 
-    custom_keyword!(__evaluated_cfgs);
-    custom_keyword!(all);
-    custom_keyword!(any);
-    custom_keyword!(cfg);
-    custom_keyword!(cfg_attr);
     custom_keyword!(clock_domain);
     custom_keyword!(connect_inexact);
     custom_keyword!(custom_bounds);
@@ -87,7 +74,6 @@ mod kw {
     custom_keyword!(no_reset);
     custom_keyword!(no_runtime_generics);
     custom_keyword!(no_static);
-    custom_keyword!(not);
     custom_keyword!(outline_generated);
     custom_keyword!(output);
     custom_keyword!(reg_builder);
@@ -864,7 +850,6 @@ macro_rules! options {
     };
 }
 
-use crate::hdl_type_alias::hdl_type_alias_impl;
 pub(crate) use options;
 
 pub(crate) fn outline_generated(contents: TokenStream, prefix: &str) -> TokenStream {
@@ -914,362 +899,21 @@ fn hdl_module_impl(item: ItemFn) -> syn::Result<TokenStream> {
     Ok(contents)
 }
 
-#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub fn hdl_module(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-pub(crate) enum CfgExpr {
+    let kw = kw::hdl_module::default();
-    Option {
+    hdl_module_impl(syn::parse2(quote! { #[#kw(#attr)] #item })?)
-        ident: Ident,
-        value: Option<(Token![=], LitStr)>,
-    },
-    All {
-        all: kw::all,
-        paren: Paren,
-        exprs: Punctuated<CfgExpr, Token![,]>,
-    },
-    Any {
-        any: kw::any,
-        paren: Paren,
-        exprs: Punctuated<CfgExpr, Token![,]>,
-    },
-    Not {
-        not: kw::not,
-        paren: Paren,
-        expr: Box<CfgExpr>,
-        trailing_comma: Option<Token![,]>,
-    },
 }
 
-impl Parse for CfgExpr {
+pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
+    let kw = kw::hdl::default();
-        match input.cursor().ident() {
+    let item = syn::parse2::<Item>(quote! { #[#kw(#attr)] #item })?;
-            Some((_, cursor)) if cursor.eof() => {
-                return Ok(CfgExpr::Option {
-                    ident: input.call(Ident::parse_any)?,
-                    value: None,
-                });
-            }
-            _ => {}
-        }
-        if input.peek(Ident::peek_any) && input.peek2(Token![=]) {
-            return Ok(CfgExpr::Option {
-                ident: input.call(Ident::parse_any)?,
-                value: Some((input.parse()?, input.parse()?)),
-            });
-        }
-        let contents;
-        if input.peek(kw::all) {
-            Ok(CfgExpr::All {
-                all: input.parse()?,
-                paren: parenthesized!(contents in input),
-                exprs: contents.call(Punctuated::parse_terminated)?,
-            })
-        } else if input.peek(kw::any) {
-            Ok(CfgExpr::Any {
-                any: input.parse()?,
-                paren: parenthesized!(contents in input),
-                exprs: contents.call(Punctuated::parse_terminated)?,
-            })
-        } else if input.peek(kw::not) {
-            Ok(CfgExpr::Not {
-                not: input.parse()?,
-                paren: parenthesized!(contents in input),
-                expr: contents.parse()?,
-                trailing_comma: contents.parse()?,
-            })
-        } else {
-            Err(input.error("expected cfg-pattern"))
-        }
-    }
-}
-
-impl ToTokens for CfgExpr {
-    fn to_tokens(&self, tokens: &mut TokenStream) {
-        match self {
-            CfgExpr::Option { ident, value } => {
-                ident.to_tokens(tokens);
-                if let Some((eq, value)) = value {
-                    eq.to_tokens(tokens);
-                    value.to_tokens(tokens);
-                }
-            }
-            CfgExpr::All { all, paren, exprs } => {
-                all.to_tokens(tokens);
-                paren.surround(tokens, |tokens| exprs.to_tokens(tokens));
-            }
-            CfgExpr::Any { any, paren, exprs } => {
-                any.to_tokens(tokens);
-                paren.surround(tokens, |tokens| exprs.to_tokens(tokens));
-            }
-            CfgExpr::Not {
-                not,
-                paren,
-                expr,
-                trailing_comma,
-            } => {
-                not.to_tokens(tokens);
-                paren.surround(tokens, |tokens| {
-                    expr.to_tokens(tokens);
-                    trailing_comma.to_tokens(tokens);
-                });
-            }
-        }
-    }
-}
-
-#[derive(Clone, PartialEq, Eq, Hash, Debug)]
-pub(crate) struct Cfg {
-    cfg: kw::cfg,
-    paren: Paren,
-    expr: CfgExpr,
-    trailing_comma: Option<Token![,]>,
-}
-
-impl Cfg {
-    fn parse_meta(meta: &Meta) -> syn::Result<Self> {
-        syn::parse2(meta.to_token_stream())
-    }
-}
-
-impl ToTokens for Cfg {
-    fn to_tokens(&self, tokens: &mut TokenStream) {
-        let Self {
-            cfg,
-            paren,
-            expr,
-            trailing_comma,
-        } = self;
-        cfg.to_tokens(tokens);
-        paren.surround(tokens, |tokens| {
-            expr.to_tokens(tokens);
-            trailing_comma.to_tokens(tokens);
-        });
-    }
-}
-
-impl Parse for Cfg {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        let contents;
-        Ok(Self {
-            cfg: input.parse()?,
-            paren: parenthesized!(contents in input),
-            expr: contents.parse()?,
-            trailing_comma: contents.parse()?,
-        })
-    }
-}
-
-#[derive(Clone, PartialEq, Eq, Hash, Debug)]
-pub(crate) struct CfgAttr {
-    cfg_attr: kw::cfg_attr,
-    paren: Paren,
-    expr: CfgExpr,
-    comma: Token![,],
-    attrs: Punctuated<Meta, Token![,]>,
-}
-
-impl CfgAttr {
-    pub(crate) fn to_cfg(&self) -> Cfg {
-        Cfg {
-            cfg: kw::cfg(self.cfg_attr.span),
-            paren: self.paren,
-            expr: self.expr.clone(),
-            trailing_comma: None,
-        }
-    }
-    fn parse_meta(meta: &Meta) -> syn::Result<Self> {
-        syn::parse2(meta.to_token_stream())
-    }
-}
-
-impl Parse for CfgAttr {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        let contents;
-        Ok(Self {
-            cfg_attr: input.parse()?,
-            paren: parenthesized!(contents in input),
-            expr: contents.parse()?,
-            comma: contents.parse()?,
-            attrs: contents.call(Punctuated::parse_terminated)?,
-        })
-    }
-}
-
-pub(crate) struct CfgAndValue {
-    cfg: Cfg,
-    eq_token: Token![=],
-    value: LitBool,
-}
-
-impl Parse for CfgAndValue {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        Ok(Self {
-            cfg: input.parse()?,
-            eq_token: input.parse()?,
-            value: input.parse()?,
-        })
-    }
-}
-
-pub(crate) struct Cfgs<T> {
-    pub(crate) bracket: Bracket,
-    pub(crate) cfgs_map: HashMap<Cfg, T>,
-    pub(crate) cfgs_list: Vec<Cfg>,
-}
-
-impl<T> Default for Cfgs<T> {
-    fn default() -> Self {
-        Self {
-            bracket: Default::default(),
-            cfgs_map: Default::default(),
-            cfgs_list: Default::default(),
-        }
-    }
-}
-
-impl<T> Cfgs<T> {
-    fn insert_cfg(&mut self, cfg: Cfg, value: T) {
-        match self.cfgs_map.entry(cfg) {
-            Entry::Occupied(_) => {}
-            Entry::Vacant(entry) => {
-                self.cfgs_list.push(entry.key().clone());
-                entry.insert(value);
-            }
-        }
-    }
-}
-
-impl Parse for Cfgs<bool> {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        let contents;
-        let bracket = bracketed!(contents in input);
-        let mut cfgs_map = HashMap::new();
-        let mut cfgs_list = Vec::new();
-        for CfgAndValue {
-            cfg,
-            eq_token,
-            value,
-        } in contents.call(Punctuated::<CfgAndValue, Token![,]>::parse_terminated)?
-        {
-            let _ = eq_token;
-            match cfgs_map.entry(cfg) {
-                Entry::Occupied(_) => {}
-                Entry::Vacant(entry) => {
-                    cfgs_list.push(entry.key().clone());
-                    entry.insert(value.value);
-                }
-            }
-        }
-        Ok(Self {
-            bracket,
-            cfgs_map,
-            cfgs_list,
-        })
-    }
-}
-
-impl Parse for Cfgs<()> {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
-        let contents;
-        let bracket = bracketed!(contents in input);
-        let mut cfgs_map = HashMap::new();
-        let mut cfgs_list = Vec::new();
-        for cfg in contents.call(Punctuated::<Cfg, Token![,]>::parse_terminated)? {
-            match cfgs_map.entry(cfg) {
-                Entry::Occupied(_) => {}
-                Entry::Vacant(entry) => {
-                    cfgs_list.push(entry.key().clone());
-                    entry.insert(());
-                }
-            }
-        }
-        Ok(Self {
-            bracket,
-            cfgs_map,
-            cfgs_list,
-        })
-    }
-}
-
-impl ToTokens for Cfgs<()> {
-    fn to_tokens(&self, tokens: &mut TokenStream) {
-        let Self {
-            bracket,
-            cfgs_map: _,
-            cfgs_list,
-        } = self;
-        bracket.surround(tokens, |tokens| {
-            for cfg in cfgs_list {
-                cfg.to_tokens(tokens);
-                <Token![,]>::default().to_tokens(tokens);
-            }
-        });
-    }
-}
-
-fn hdl_main(
-    kw: impl CustomToken,
-    attr: TokenStream,
-    item: TokenStream,
-) -> syn::Result<TokenStream> {
-    fn parse_evaluated_cfgs_attr<R>(
-        input: ParseStream,
-        parse_inner: impl FnOnce(ParseStream) -> syn::Result<R>,
-    ) -> syn::Result<R> {
-        let _: Token![#] = input.parse()?;
-        let bracket_content;
-        bracketed!(bracket_content in input);
-        let _: kw::__evaluated_cfgs = bracket_content.parse()?;
-        let paren_content;
-        parenthesized!(paren_content in bracket_content);
-        parse_inner(&paren_content)
-    }
-    let (evaluated_cfgs, item): (_, TokenStream) = Parser::parse2(
-        |input: ParseStream| {
-            let peek = input.fork();
-            if parse_evaluated_cfgs_attr(&peek, |_| Ok(())).is_ok() {
-                let evaluated_cfgs = parse_evaluated_cfgs_attr(input, Cfgs::<bool>::parse)?;
-                Ok((Some(evaluated_cfgs), input.parse()?))
-            } else {
-                Ok((None, input.parse()?))
-            }
-        },
-        item,
-    )?;
-    let cfgs = if let Some(cfgs) = evaluated_cfgs {
-        cfgs
-    } else {
-        let cfgs = process_cfg::collect_cfgs(syn::parse2(item.clone())?)?;
-        if cfgs.cfgs_list.is_empty() {
-            Cfgs::default()
-        } else {
-            return Ok(quote! {
-                ::fayalite::__cfg_expansion_helper! {
-                    []
-                    #cfgs
-                    {#[::fayalite::#kw(#attr)]} { #item }
-                }
-            });
-        }
-    };
-    let item = syn::parse2(quote! { #[#kw(#attr)] #item })?;
-    let Some(item) = process_cfg::process_cfgs(item, cfgs)? else {
-        return Ok(TokenStream::new());
-    };
     match item {
         Item::Enum(item) => hdl_enum::hdl_enum(item),
         Item::Struct(item) => hdl_bundle::hdl_bundle(item),
         Item::Fn(item) => hdl_module_impl(item),
-        Item::Type(item) => hdl_type_alias_impl(item),
         _ => Err(syn::Error::new(
             Span::call_site(),
-            "top-level #[hdl] can only be used on structs, enums, type aliases, or functions",
+            "top-level #[hdl] can only be used on structs, enums, or functions",
         )),
     }
 }
-
-pub fn hdl_module(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-    hdl_main(kw::hdl_module::default(), attr, item)
-}
-
-pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-    hdl_main(kw::hdl::default(), attr, item)
-}

crates/fayalite/Cargo.toml

@@ -25,11 +25,9 @@ jobslot.workspace = true
 num-bigint.workspace = true
 num-traits.workspace = true
 os_pipe.workspace = true
-petgraph.workspace = true
 serde_json.workspace = true
 serde.workspace = true
 tempfile.workspace = true
-vec_map.workspace = true
 which.workspace = true
 
 [dev-dependencies]

crates/fayalite/build.rs

@@ -5,9 +5,6 @@ use std::{env, fs, path::Path};
 
 fn main() {
     println!("cargo::rustc-check-cfg=cfg(todo)");
-    println!("cargo::rustc-check-cfg=cfg(cfg_false_for_tests)");
-    println!("cargo::rustc-check-cfg=cfg(cfg_true_for_tests)");
-    println!("cargo::rustc-cfg=cfg_true_for_tests");
     let path = "visit_types.json";
     println!("cargo::rerun-if-changed={path}");
     println!("cargo::rerun-if-changed=build.rs");

crates/fayalite/src/bundle.rs

@@ -4,14 +4,12 @@
 use crate::{
     expr::{ops::BundleLiteral, Expr, ToExpr},
     intern::{Intern, Interned},
-    sim::{SimValue, ToSimValue},
     source_location::SourceLocation,
     ty::{
         impl_match_variant_as_self, CanonicalType, MatchVariantWithoutScope, StaticType, Type,
         TypeProperties, TypeWithDeref,
     },
 };
-use bitvec::vec::BitVec;
 use hashbrown::HashMap;
 use std::{fmt, marker::PhantomData};
 
@@ -325,7 +323,7 @@ macro_rules! impl_tuple_builder_fields {
 }
 
 macro_rules! impl_tuples {
-    ([$({#[num = $num:literal, field = $field:ident, ty = $ty_var:ident: $Ty:ident] $var:ident: $T:ident})*] []) => {
+    ([$({#[num = $num:literal, field = $field:ident] $var:ident: $T:ident})*] []) => {
         impl_tuple_builder_fields! {
             {}
             [$({
@@ -425,79 +423,6 @@ macro_rules! impl_tuples {
                 BundleLiteral::new(ty, field_values[..].intern()).to_expr()
             }
         }
-        impl<$($T: ToSimValue<CanonicalType>,)*> ToSimValue<CanonicalType> for ($($T,)*) {
-            #[track_caller]
-            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                ToSimValue::<Bundle>::to_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
-            }
-            #[track_caller]
-            fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType>
-            {
-                ToSimValue::<Bundle>::into_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
-            }
-            #[track_caller]
-            fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
-                ToSimValue::<Bundle>::box_into_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
-            }
-        }
-        impl<$($T: ToSimValue<CanonicalType>,)*> ToSimValue<Bundle> for ($($T,)*) {
-            #[track_caller]
-            fn to_sim_value(&self, ty: Bundle) -> SimValue<Bundle> {
-                let ($($var,)*) = self;
-                let [$($ty_var,)*] = *ty.fields() else {
-                    panic!("bundle has wrong number of fields");
-                };
-                $(let $var = $var.to_sim_value($ty_var.ty);)*
-                ToSimValue::into_sim_value(($($var,)*), ty)
-            }
-            #[track_caller]
-            fn into_sim_value(self, ty: Bundle) -> SimValue<Bundle> {
-                #![allow(unused_mut)]
-                #![allow(clippy::unused_unit)]
-                let ($($var,)*) = self;
-                let [$($ty_var,)*] = *ty.fields() else {
-                    panic!("bundle has wrong number of fields");
-                };
-                let mut bits: Option<BitVec> = None;
-                $(let $var = $var.into_sim_value($ty_var.ty);
-                assert_eq!($var.ty(), $ty_var.ty);
-                if !$var.bits().is_empty() {
-                    if let Some(bits) = &mut bits {
-                        bits.extend_from_bitslice($var.bits());
-                    } else {
-                        let mut $var = $var.into_bits();
-                        $var.reserve(ty.type_properties().bit_width - $var.len());
-                        bits = Some($var);
-                    }
-                }
-                )*
-                bits.unwrap_or_else(BitVec::new).into_sim_value(ty)
-            }
-            #[track_caller]
-            fn box_into_sim_value(self: Box<Self>, ty: Bundle) -> SimValue<Bundle> {
-                Self::into_sim_value(*self, ty)
-            }
-        }
-        impl<$($T: ToSimValue<$Ty>, $Ty: Type,)*> ToSimValue<($($Ty,)*)> for ($($T,)*) {
-            #[track_caller]
-            fn to_sim_value(&self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
-                let ($($var,)*) = self;
-                let ($($ty_var,)*) = ty;
-                $(let $var = $var.to_sim_value($ty_var).into_canonical();)*
-                SimValue::from_canonical(ToSimValue::into_sim_value(($($var,)*), ty.canonical()))
-            }
-            #[track_caller]
-            fn into_sim_value(self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
-                let ($($var,)*) = self;
-                let ($($ty_var,)*) = ty;
-                $(let $var = $var.into_sim_value($ty_var).into_canonical();)*
-                SimValue::from_canonical(ToSimValue::into_sim_value(($($var,)*), ty.canonical()))
-            }
-            #[track_caller]
-            fn box_into_sim_value(self: Box<Self>, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
-                Self::into_sim_value(*self, ty)
-            }
-        }
     };
     ([$($lhs:tt)*] [$rhs_first:tt $($rhs:tt)*]) => {
         impl_tuples!([$($lhs)*] []);
@@ -507,18 +432,18 @@ macro_rules! impl_tuples {
 
 impl_tuples! {
     [] [
-        {#[num = 0, field = field_0, ty = ty0: Ty0] v0: T0}
+        {#[num = 0, field = field_0] v0: T0}
-        {#[num = 1, field = field_1, ty = ty1: Ty1] v1: T1}
+        {#[num = 1, field = field_1] v1: T1}
-        {#[num = 2, field = field_2, ty = ty2: Ty2] v2: T2}
+        {#[num = 2, field = field_2] v2: T2}
-        {#[num = 3, field = field_3, ty = ty3: Ty3] v3: T3}
+        {#[num = 3, field = field_3] v3: T3}
-        {#[num = 4, field = field_4, ty = ty4: Ty4] v4: T4}
+        {#[num = 4, field = field_4] v4: T4}
-        {#[num = 5, field = field_5, ty = ty5: Ty5] v5: T5}
+        {#[num = 5, field = field_5] v5: T5}
-        {#[num = 6, field = field_6, ty = ty6: Ty6] v6: T6}
+        {#[num = 6, field = field_6] v6: T6}
-        {#[num = 7, field = field_7, ty = ty7: Ty7] v7: T7}
+        {#[num = 7, field = field_7] v7: T7}
-        {#[num = 8, field = field_8, ty = ty8: Ty8] v8: T8}
+        {#[num = 8, field = field_8] v8: T8}
-        {#[num = 9, field = field_9, ty = ty9: Ty9] v9: T9}
+        {#[num = 9, field = field_9] v9: T9}
-        {#[num = 10, field = field_10, ty = ty10: Ty10] v10: T10}
+        {#[num = 10, field = field_10] v10: T10}
-        {#[num = 11, field = field_11, ty = ty11: Ty11] v11: T11}
+        {#[num = 11, field = field_11] v11: T11}
     ]
 }
 
@@ -603,27 +528,3 @@ impl<T: ?Sized + Send + Sync + 'static> ToExpr for PhantomData<T> {
         BundleLiteral::new(PhantomData, Interned::default()).to_expr()
     }
 }
-
-impl<T: ?Sized + Send + Sync + 'static> ToSimValue<Self> for PhantomData<T> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: Self) -> SimValue<Self> {
-        ToSimValue::into_sim_value(BitVec::new(), ty)
-    }
-}
-
-impl<T: ?Sized> ToSimValue<Bundle> for PhantomData<T> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: Bundle) -> SimValue<Bundle> {
-        assert!(ty.fields().is_empty());
-        ToSimValue::into_sim_value(BitVec::new(), ty)
-    }
-}
-
-impl<T: ?Sized> ToSimValue<CanonicalType> for PhantomData<T> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        let ty = Bundle::from_canonical(ty);
-        assert!(ty.fields().is_empty());
-        ToSimValue::into_sim_value(BitVec::new(), ty).into_canonical()
-    }
-}

crates/fayalite/src/cli.rs

@@ -653,19 +653,21 @@ impl FormalArgs {
                 self.sby.display()
             )))
         };
-        fs::write(
+        if do_cache {
-            cache_file,
+            fs::write(
-            serde_json::to_string_pretty(&FormalCache {
+                cache_file,
-                version: FormalCacheVersion::CURRENT,
+                serde_json::to_string_pretty(&FormalCache {
-                contents_hash: contents_hash.unwrap(),
+                    version: FormalCacheVersion::CURRENT,
-                stdout_stderr: captured_output,
+                    contents_hash: contents_hash.unwrap(),
-                result: match &result {
+                    stdout_stderr: captured_output,
-                    Ok(FormalOutput { verilog: _ }) => Ok(FormalCacheOutput {}),
+                    result: match &result {
-                    Err(error) => Err(error.to_string()),
+                        Ok(FormalOutput { verilog: _ }) => Ok(FormalCacheOutput {}),
-                },
+                        Err(error) => Err(error.to_string()),
-            })
+                    },
-            .expect("serialization shouldn't ever fail"),
+                })
-        )?;
+                .expect("serialization shouldn't ever fail"),
+            )?;
+        }
         result
     }
 }

crates/fayalite/src/clock.rs

@@ -4,7 +4,7 @@ use crate::{
     expr::{Expr, ToExpr},
     hdl,
     int::Bool,
-    reset::{Reset, ResetType},
+    reset::Reset,
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
 };
@@ -88,9 +88,9 @@ impl ToClock for Expr<Clock> {
 }
 
 #[hdl]
-pub struct ClockDomain<R: ResetType = Reset> {
+pub struct ClockDomain {
     pub clk: Clock,
-    pub rst: R,
+    pub rst: Reset,
 }
 
 impl ToClock for bool {

crates/fayalite/src/expr.rs

@@ -17,7 +17,6 @@ use crate::{
         Instance, ModuleIO,
     },
     reg::Reg,
-    reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
     ty::{CanonicalType, StaticType, Type, TypeWithDeref},
     wire::Wire,
 };
@@ -210,9 +209,7 @@ expr_enum! {
         ModuleIO(ModuleIO<CanonicalType>),
         Instance(Instance<Bundle>),
         Wire(Wire<CanonicalType>),
-        Reg(Reg<CanonicalType, Reset>),
+        Reg(Reg<CanonicalType>),
-        RegSync(Reg<CanonicalType, SyncReset>),
-        RegAsync(Reg<CanonicalType, AsyncReset>),
         MemPort(MemPort<DynPortType>),
     }
 }
@@ -596,42 +593,25 @@ impl<T: Type> GetTarget for Wire<T> {
     }
 }
 
-impl<T: Type, R: ResetType> ToExpr for Reg<T, R> {
+impl<T: Type> ToExpr for Reg<T> {
     type Type = T;
 
     fn to_expr(&self) -> Expr<Self::Type> {
-        struct Dispatch;
-        impl ResetTypeDispatch for Dispatch {
-            type Input<T: ResetType> = Reg<CanonicalType, T>;
-            type Output<T: ResetType> = ExprEnum;
-
-            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
-                ExprEnum::Reg(input)
-            }
-
-            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
-                ExprEnum::RegSync(input)
-            }
-
-            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
-                ExprEnum::RegAsync(input)
-            }
-        }
         Expr {
-            __enum: R::dispatch(self.canonical(), Dispatch).intern_sized(),
+            __enum: ExprEnum::Reg(self.canonical()).intern_sized(),
             __ty: self.ty(),
             __flow: self.flow(),
         }
     }
 }
 
-impl<T: Type, R: ResetType> ToLiteralBits for Reg<T, R> {
+impl<T: Type> ToLiteralBits for Reg<T> {
     fn to_literal_bits(&self) -> Result<Interned<BitSlice>, NotALiteralExpr> {
         Err(NotALiteralExpr)
     }
 }
 
-impl<T: Type, R: ResetType> GetTarget for Reg<T, R> {
+impl<T: Type> GetTarget for Reg<T> {
     fn target(&self) -> Option<Interned<Target>> {
         Some(Intern::intern_sized(self.canonical().into()))
     }

crates/fayalite/src/expr/ops.rs

@@ -19,10 +19,7 @@ use crate::{
         UIntType, UIntValue,
     },
     intern::{Intern, Interned},
-    reset::{
+    reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
-        AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset, ToAsyncReset, ToReset,
-        ToSyncReset,
-    },
     ty::{CanonicalType, StaticType, Type},
     util::ConstUsize,
 };
@@ -265,7 +262,7 @@ impl Neg {
         };
         let result_ty = retval.ty();
         retval.literal_bits = arg.to_literal_bits().map(|bits| {
-            Intern::intern_owned(result_ty.bits_from_bigint_wrapping(&-SInt::bits_to_bigint(&bits)))
+            Intern::intern_owned(result_ty.bits_from_bigint_wrapping(-SInt::bits_to_bigint(&bits)))
         });
         retval
     }
@@ -372,7 +369,7 @@ fn binary_op_literal_bits<ResultTy: BoolOrIntType, Lhs: BoolOrIntType, Rhs: Bool
     let rhs = Rhs::bits_to_bigint(&rhs);
     let result = f(lhs, rhs)?;
     Ok(Intern::intern_owned(
-        result_ty.bits_from_bigint_wrapping(&result),
+        result_ty.bits_from_bigint_wrapping(result),
     ))
 }
 
@@ -1347,7 +1344,7 @@ macro_rules! binary_op_fixed_shift {
                     literal_bits: Err(NotALiteralExpr),
                 };
                 retval.literal_bits = lhs.to_literal_bits().map(|bits| {
-                    Intern::intern_owned(retval.ty().bits_from_bigint_wrapping(&$Trait::$method(
+                    Intern::intern_owned(retval.ty().bits_from_bigint_wrapping($Trait::$method(
                         $ty::bits_to_bigint(&bits),
                         rhs,
                     )))
@@ -1624,7 +1621,7 @@ macro_rules! impl_cast_int_op {
                     ty,
                     literal_bits: arg.to_literal_bits().map(|bits| {
                         Intern::intern_owned(
-                            ty.bits_from_bigint_wrapping(&$from::bits_to_bigint(&bits)),
+                            ty.bits_from_bigint_wrapping($from::bits_to_bigint(&bits)),
                         )
                     }),
                 }
@@ -1776,11 +1773,11 @@ impl_cast_bit_op!(CastSIntToAsyncReset, SInt<1>, #[dyn] SInt, AsyncReset, #[trai
 impl_cast_bit_op!(CastSyncResetToBool, SyncReset, Bool);
 impl_cast_bit_op!(CastSyncResetToUInt, SyncReset, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastSyncResetToSInt, SyncReset, SInt<1>, #[dyn] SInt);
-impl_cast_bit_op!(CastSyncResetToReset, SyncReset, Reset);
+impl_cast_bit_op!(CastSyncResetToReset, SyncReset, Reset, #[trait] ToReset::to_reset);
 impl_cast_bit_op!(CastAsyncResetToBool, AsyncReset, Bool);
 impl_cast_bit_op!(CastAsyncResetToUInt, AsyncReset, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastAsyncResetToSInt, AsyncReset, SInt<1>, #[dyn] SInt);
-impl_cast_bit_op!(CastAsyncResetToReset, AsyncReset, Reset);
+impl_cast_bit_op!(CastAsyncResetToReset, AsyncReset, Reset, #[trait] ToReset::to_reset);
 impl_cast_bit_op!(CastResetToBool, Reset, Bool);
 impl_cast_bit_op!(CastResetToUInt, Reset, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastResetToSInt, Reset, SInt<1>, #[dyn] SInt);
@@ -1791,107 +1788,6 @@ impl_cast_bit_op!(CastClockToBool, Clock, Bool);
 impl_cast_bit_op!(CastClockToUInt, Clock, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastClockToSInt, Clock, SInt<1>, #[dyn] SInt);
 
-impl<T: ResetType> ToReset for Expr<T> {
-    fn to_reset(&self) -> Expr<Reset> {
-        struct Dispatch;
-        impl ResetTypeDispatch for Dispatch {
-            type Input<T: ResetType> = Expr<T>;
-            type Output<T: ResetType> = Expr<Reset>;
-
-            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
-                input
-            }
-
-            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
-                input.cast_to_static()
-            }
-
-            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
-                input.cast_to_static()
-            }
-        }
-        T::dispatch(*self, Dispatch)
-    }
-}
-
-impl ExprCastTo<AsyncReset> for AsyncReset {
-    fn cast_to(src: Expr<Self>, _to_type: AsyncReset) -> Expr<AsyncReset> {
-        src
-    }
-}
-
-impl ExprCastTo<SyncReset> for AsyncReset {
-    fn cast_to(src: Expr<Self>, to_type: SyncReset) -> Expr<SyncReset> {
-        src.cast_to(Bool).cast_to(to_type)
-    }
-}
-
-impl ExprCastTo<Clock> for AsyncReset {
-    fn cast_to(src: Expr<Self>, to_type: Clock) -> Expr<Clock> {
-        src.cast_to(Bool).cast_to(to_type)
-    }
-}
-
-impl ExprCastTo<AsyncReset> for SyncReset {
-    fn cast_to(src: Expr<Self>, to_type: AsyncReset) -> Expr<AsyncReset> {
-        src.cast_to(Bool).cast_to(to_type)
-    }
-}
-
-impl ExprCastTo<SyncReset> for SyncReset {
-    fn cast_to(src: Expr<Self>, _to_type: SyncReset) -> Expr<SyncReset> {
-        src
-    }
-}
-
-impl ExprCastTo<Clock> for SyncReset {
-    fn cast_to(src: Expr<Self>, to_type: Clock) -> Expr<Clock> {
-        src.cast_to(Bool).cast_to(to_type)
-    }
-}
-
-impl ExprCastTo<AsyncReset> for Reset {
-    fn cast_to(src: Expr<Self>, to_type: AsyncReset) -> Expr<AsyncReset> {
-        src.cast_to(Bool).cast_to(to_type)
-    }
-}
-
-impl ExprCastTo<SyncReset> for Reset {
-    fn cast_to(src: Expr<Self>, to_type: SyncReset) -> Expr<SyncReset> {
-        src.cast_to(Bool).cast_to(to_type)
-    }
-}
-
-impl ExprCastTo<Reset> for Reset {
-    fn cast_to(src: Expr<Self>, _to_type: Reset) -> Expr<Reset> {
-        src
-    }
-}
-
-impl ExprCastTo<Clock> for Reset {
-    fn cast_to(src: Expr<Self>, to_type: Clock) -> Expr<Clock> {
-        src.cast_to(Bool).cast_to(to_type)
-    }
-}
-
-impl ExprCastTo<AsyncReset> for Clock {
-    fn cast_to(src: Expr<Self>, to_type: AsyncReset) -> Expr<AsyncReset> {
-        src.cast_to(Bool).cast_to(to_type)
-    }
-}
-
-impl ExprCastTo<SyncReset> for Clock {
-    fn cast_to(src: Expr<Self>, to_type: SyncReset) -> Expr<SyncReset> {
-        src.cast_to(Bool).cast_to(to_type)
-    }
-}
-
-impl ExprCastTo<Clock> for Clock {
-    fn cast_to(src: Expr<Self>, _to_type: Clock) -> Expr<Clock> {
-        src
-    }
-}
-
 #[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct FieldAccess<FieldType: Type = CanonicalType> {
     base: Expr<Bundle>,

crates/fayalite/src/expr/target.rs

@@ -3,19 +3,18 @@
 use crate::{
     array::Array,
     bundle::{Bundle, BundleField},
-    expr::{Expr, Flow, ToExpr},
+    expr::Flow,
     intern::{Intern, Interned},
     memory::{DynPortType, MemPort},
     module::{Instance, ModuleIO, TargetName},
     reg::Reg,
-    reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     wire::Wire,
 };
 use std::fmt;
 
-#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Clone, PartialEq, Eq, Hash)]
 pub struct TargetPathBundleField {
     pub name: Interned<str>,
 }
@@ -26,7 +25,7 @@ impl fmt::Display for TargetPathBundleField {
     }
 }
 
-#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Clone, PartialEq, Eq, Hash)]
 pub struct TargetPathArrayElement {
     pub index: usize,
 }
@@ -37,7 +36,7 @@ impl fmt::Display for TargetPathArrayElement {
     }
 }
 
-#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Clone, PartialEq, Eq, Hash)]
 pub struct TargetPathDynArrayElement {}
 
 impl fmt::Display for TargetPathDynArrayElement {
@@ -46,7 +45,7 @@ impl fmt::Display for TargetPathDynArrayElement {
     }
 }
 
-#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Clone, PartialEq, Eq, Hash)]
 pub enum TargetPathElement {
     BundleField(TargetPathBundleField),
     ArrayElement(TargetPathArrayElement),
@@ -128,7 +127,6 @@ macro_rules! impl_target_base {
         $(#[$enum_meta:meta])*
         $enum_vis:vis enum $TargetBase:ident {
             $(
-                $(#[from = $from:ident])?
                 #[is = $is_fn:ident]
                 #[to = $to_fn:ident]
                 $(#[$variant_meta:meta])*
@@ -152,19 +150,19 @@ macro_rules! impl_target_base {
             }
         }
 
-        $($(
+        $(
         impl From<$VariantTy> for $TargetBase {
-            fn $from(value: $VariantTy) -> Self {
+            fn from(value: $VariantTy) -> Self {
                 Self::$Variant(value)
             }
         }
 
         impl From<$VariantTy> for Target {
-            fn $from(value: $VariantTy) -> Self {
+            fn from(value: $VariantTy) -> Self {
                 $TargetBase::$Variant(value).into()
             }
         }
-        )*)?
+        )*
 
         impl $TargetBase {
             $(
@@ -195,79 +193,30 @@ macro_rules! impl_target_base {
                 }
             }
         }
-
-        impl ToExpr for $TargetBase {
-            type Type = CanonicalType;
-
-            fn to_expr(&self) -> Expr<Self::Type> {
-                match self {
-                    $(Self::$Variant(v) => Expr::canonical(v.to_expr()),)*
-                }
-            }
-        }
     };
 }
 
 impl_target_base! {
-    #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+    #[derive(Clone, PartialEq, Eq, Hash)]
     pub enum TargetBase {
-        #[from = from]
         #[is = is_module_io]
         #[to = module_io]
         ModuleIO(ModuleIO<CanonicalType>),
-        #[from = from]
         #[is = is_mem_port]
         #[to = mem_port]
         MemPort(MemPort<DynPortType>),
         #[is = is_reg]
         #[to = reg]
-        Reg(Reg<CanonicalType, Reset>),
+        Reg(Reg<CanonicalType>),
-        #[is = is_reg_sync]
-        #[to = reg_sync]
-        RegSync(Reg<CanonicalType, SyncReset>),
-        #[is = is_reg_async]
-        #[to = reg_async]
-        RegAsync(Reg<CanonicalType, AsyncReset>),
-        #[from = from]
         #[is = is_wire]
         #[to = wire]
         Wire(Wire<CanonicalType>),
-        #[from = from]
         #[is = is_instance]
         #[to = instance]
         Instance(Instance<Bundle>),
     }
 }
 
-impl<R: ResetType> From<Reg<CanonicalType, R>> for TargetBase {
-    fn from(value: Reg<CanonicalType, R>) -> Self {
-        struct Dispatch;
-        impl ResetTypeDispatch for Dispatch {
-            type Input<T: ResetType> = Reg<CanonicalType, T>;
-            type Output<T: ResetType> = TargetBase;
-
-            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
-                TargetBase::Reg(input)
-            }
-
-            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
-                TargetBase::RegSync(input)
-            }
-
-            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
-                TargetBase::RegAsync(input)
-            }
-        }
-        R::dispatch(value, Dispatch)
-    }
-}
-
-impl<R: ResetType> From<Reg<CanonicalType, R>> for Target {
-    fn from(value: Reg<CanonicalType, R>) -> Self {
-        TargetBase::from(value).into()
-    }
-}
-
 impl fmt::Display for TargetBase {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         write!(f, "{:?}", self.target_name())
@@ -280,8 +229,6 @@ impl TargetBase {
             TargetBase::ModuleIO(v) => TargetName(v.scoped_name(), None),
             TargetBase::MemPort(v) => TargetName(v.mem_name(), Some(v.port_name())),
             TargetBase::Reg(v) => TargetName(v.scoped_name(), None),
-            TargetBase::RegSync(v) => TargetName(v.scoped_name(), None),
-            TargetBase::RegAsync(v) => TargetName(v.scoped_name(), None),
             TargetBase::Wire(v) => TargetName(v.scoped_name(), None),
             TargetBase::Instance(v) => TargetName(v.scoped_name(), None),
         }
@@ -291,8 +238,6 @@ impl TargetBase {
             TargetBase::ModuleIO(v) => v.ty(),
             TargetBase::MemPort(v) => v.ty().canonical(),
             TargetBase::Reg(v) => v.ty(),
-            TargetBase::RegSync(v) => v.ty(),
-            TargetBase::RegAsync(v) => v.ty(),
             TargetBase::Wire(v) => v.ty(),
             TargetBase::Instance(v) => v.ty().canonical(),
         }
@@ -368,7 +313,7 @@ impl TargetChild {
     }
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+#[derive(Clone, PartialEq, Eq, Hash)]
 pub enum Target {
     Base(Interned<TargetBase>),
     Child(TargetChild),

crates/fayalite/src/firrtl.rs

@@ -31,7 +31,7 @@ use crate::{
         StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg,
         StmtWire,
     },
-    reset::{AsyncReset, Reset, ResetType, SyncReset},
+    reset::{AsyncReset, Reset, SyncReset},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     util::{
@@ -1739,14 +1739,6 @@ impl<'a> Exporter<'a> {
                 assert!(!const_ty, "not a constant");
                 self.module.ns.get(expr.scoped_name().1).to_string()
             }
-            ExprEnum::RegSync(expr) => {
-                assert!(!const_ty, "not a constant");
-                self.module.ns.get(expr.scoped_name().1).to_string()
-            }
-            ExprEnum::RegAsync(expr) => {
-                assert!(!const_ty, "not a constant");
-                self.module.ns.get(expr.scoped_name().1).to_string()
-            }
             ExprEnum::MemPort(expr) => {
                 assert!(!const_ty, "not a constant");
                 let mem_name = self.module.ns.get(expr.mem_name().1);
@@ -1856,8 +1848,6 @@ impl<'a> Exporter<'a> {
                         self.module.ns.get(v.mem_name().1)
                     }
                     TargetBase::Reg(v) => self.module.ns.get(v.name_id()),
-                    TargetBase::RegSync(v) => self.module.ns.get(v.name_id()),
-                    TargetBase::RegAsync(v) => self.module.ns.get(v.name_id()),
                     TargetBase::Wire(v) => self.module.ns.get(v.name_id()),
                     TargetBase::Instance(v) => self.module.ns.get(v.name_id()),
                 };
@@ -1966,37 +1956,6 @@ impl<'a> Exporter<'a> {
         drop(memory_indent);
         Ok(body)
     }
-    fn stmt_reg<R: ResetType>(
-        &mut self,
-        stmt_reg: StmtReg<R>,
-        module_name: Ident,
-        definitions: &RcDefinitions,
-        body: &mut String,
-    ) {
-        let StmtReg { annotations, reg } = stmt_reg;
-        let indent = self.indent;
-        self.targeted_annotations(module_name, vec![], &annotations);
-        let name = self.module.ns.get(reg.name_id());
-        let ty = self.type_state.ty(reg.ty());
-        let clk = self.expr(Expr::canonical(reg.clock_domain().clk), definitions, false);
-        if let Some(init) = reg.init() {
-            let rst = self.expr(Expr::canonical(reg.clock_domain().rst), definitions, false);
-            let init = self.expr(init, definitions, false);
-            writeln!(
-                body,
-                "{indent}regreset {name}: {ty}, {clk}, {rst}, {init}{}",
-                FileInfo::new(reg.source_location()),
-            )
-            .unwrap();
-        } else {
-            writeln!(
-                body,
-                "{indent}reg {name}: {ty}, {clk}{}",
-                FileInfo::new(reg.source_location()),
-            )
-            .unwrap();
-        }
-    }
     fn block(
         &mut self,
         module: Interned<Module<Bundle>>,
@@ -2167,14 +2126,30 @@ impl<'a> Exporter<'a> {
                     )
                     .unwrap();
                 }
-                Stmt::Declaration(StmtDeclaration::Reg(stmt_reg)) => {
+                Stmt::Declaration(StmtDeclaration::Reg(StmtReg { annotations, reg })) => {
-                    self.stmt_reg(stmt_reg, module_name, &definitions, &mut body);
+                    self.targeted_annotations(module_name, vec![], &annotations);
-                }
+                    let name = self.module.ns.get(reg.name_id());
-                Stmt::Declaration(StmtDeclaration::RegSync(stmt_reg)) => {
+                    let ty = self.type_state.ty(reg.ty());
-                    self.stmt_reg(stmt_reg, module_name, &definitions, &mut body);
+                    let clk =
-                }
+                        self.expr(Expr::canonical(reg.clock_domain().clk), &definitions, false);
-                Stmt::Declaration(StmtDeclaration::RegAsync(stmt_reg)) => {
+                    if let Some(init) = reg.init() {
-                    self.stmt_reg(stmt_reg, module_name, &definitions, &mut body);
+                        let rst =
+                            self.expr(Expr::canonical(reg.clock_domain().rst), &definitions, false);
+                        let init = self.expr(init, &definitions, false);
+                        writeln!(
+                            body,
+                            "{indent}regreset {name}: {ty}, {clk}, {rst}, {init}{}",
+                            FileInfo::new(reg.source_location()),
+                        )
+                        .unwrap();
+                    } else {
+                        writeln!(
+                            body,
+                            "{indent}reg {name}: {ty}, {clk}{}",
+                            FileInfo::new(reg.source_location()),
+                        )
+                        .unwrap();
+                    }
                 }
                 Stmt::Declaration(StmtDeclaration::Instance(StmtInstance {
                     annotations,

crates/fayalite/src/int.rs

@@ -202,17 +202,17 @@ macro_rules! impl_int {
                     bit_width: self.width(),
                 }
             }
-            pub fn bits_from_bigint_wrapping(self, v: &BigInt) -> BitVec {
+            pub fn bits_from_bigint_wrapping(self, v: BigInt) -> BitVec {
                 BoolOrIntType::bits_from_bigint_wrapping(self, v)
             }
-            pub fn from_bigint_wrapping(self, v: &BigInt) -> $value<Width> {
+            pub fn from_bigint_wrapping(self, v: BigInt) -> $value<Width> {
                 $value {
                     bits: Arc::new(self.bits_from_bigint_wrapping(v)),
                     _phantom: PhantomData,
                 }
             }
             pub fn from_int_wrapping(self, v: impl Into<BigInt>) -> $value<Width> {
-                self.from_bigint_wrapping(&v.into())
+                self.from_bigint_wrapping(v.into())
             }
             pub fn zero(self) -> $value<Width> {
                 self.from_int_wrapping(0u8)
@@ -227,29 +227,12 @@ macro_rules! impl_int {
         impl<Width: Size> BoolOrIntType for $name<Width> {
             type Width = Width;
             type Signed = ConstBool<$SIGNED>;
-            type Value = $value<Width>;
             fn width(self) -> usize {
                 $name::width(self)
             }
             fn new(width: Width::SizeType) -> Self {
                 $name { width }
             }
-            fn value_from_bigint_wrapping(self, v: &BigInt) -> Self::Value {
-                $value::<Width>::from_bigint_wrapping(self, v)
-            }
-            fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value {
-                #[derive(Copy, Clone, Eq, PartialEq, Hash)]
-                struct MemoizeBitsToValue;
-                impl Memoize for MemoizeBitsToValue {
-                    type Input = BitSlice;
-                    type InputOwned = BitVec;
-                    type Output = Arc<BitVec>;
-                    fn inner(self, input: &Self::Input) -> Self::Output {
-                        Arc::new(input.to_bitvec())
-                    }
-                }
-                $value::new(MemoizeBitsToValue.get_cow(bits))
-            }
             fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self> {
                 #[derive(Copy, Clone, Eq, PartialEq, Hash)]
                 struct MemoizeBitsToExpr;
@@ -351,24 +334,6 @@ macro_rules! impl_int {
             }
         }
 
-        impl<Width: Size> PartialOrd for $value<Width> {
-            fn partial_cmp(&self, other: &Self) -> Option<std::cmp::Ordering> {
-                Some(self.cmp(other))
-            }
-        }
-
-        impl<Width: Size> Ord for $value<Width> {
-            fn cmp(&self, other: &Self) -> std::cmp::Ordering {
-                self.to_bigint().cmp(&other.to_bigint())
-            }
-        }
-
-        impl<Width: Size> From<$value<Width>> for BigInt {
-            fn from(v: $value<Width>) -> BigInt {
-                v.to_bigint()
-            }
-        }
-
         impl<Width: Size> $value<Width> {
             pub fn width(&self) -> usize {
                 if let Some(retval) = Width::KNOWN_VALUE {
@@ -378,7 +343,7 @@ macro_rules! impl_int {
                     self.bits.len()
                 }
             }
-            pub fn from_bigint_wrapping(ty: $name<Width>, v: &BigInt) -> $value<Width> {
+            pub fn from_bigint_wrapping(ty: $name<Width>, v: BigInt) -> $value<Width> {
                 ty.from_bigint_wrapping(v)
             }
             pub fn to_bigint(&self) -> BigInt {
@@ -488,10 +453,7 @@ impl SInt {
                     v.not().bits().checked_add(1).expect("too big")
                 }
                 Sign::NoSign => 0,
-                Sign::Plus => {
+                Sign::Plus => v.bits(),
-                    // account for sign bit
-                    v.bits().checked_add(1).expect("too big")
-                }
             }
             .try_into()
             .expect("too big"),
@@ -520,19 +482,6 @@ macro_rules! impl_prim_int {
         $(#[$meta:meta])*
         $prim_int:ident, $ty:ty
     ) => {
-        impl From<$prim_int> for <$ty as BoolOrIntType>::Value {
-            fn from(v: $prim_int) -> Self {
-                <$ty>::le_bytes_to_value_wrapping(
-                    &v.to_le_bytes(),
-                    <$ty as BoolOrIntType>::Width::VALUE,
-                )
-            }
-        }
-        impl From<NonZero<$prim_int>> for <$ty as BoolOrIntType>::Value {
-            fn from(v: NonZero<$prim_int>) -> Self {
-                v.get().into()
-            }
-        }
         $(#[$meta])*
         impl ToExpr for $prim_int {
             type Type = $ty;
@@ -549,7 +498,10 @@ macro_rules! impl_prim_int {
             type Type = $ty;
 
             fn to_expr(&self) -> Expr<Self::Type> {
-                self.get().to_expr()
+                <$ty>::le_bytes_to_expr_wrapping(
+                    &self.get().to_le_bytes(),
+                    <$ty as BoolOrIntType>::Width::VALUE,
+                )
             }
         }
     };
@@ -579,15 +531,6 @@ impl_prim_int!(
 pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
     type Width: Size;
     type Signed: GenericConstBool;
-    type Value: Clone
-        + Ord
-        + std::hash::Hash
-        + fmt::Debug
-        + Send
-        + Sync
-        + 'static
-        + ToExpr<Type = Self>
-        + Into<BigInt>;
     fn width(self) -> usize;
     fn new(width: <Self::Width as Size>::SizeType) -> Self;
     fn new_static() -> Self
@@ -602,24 +545,17 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
     fn as_same_width_uint(self) -> UIntType<Self::Width> {
         UIntType::new(Self::Width::from_usize(self.width()))
     }
-    fn value_from_int_wrapping(self, v: impl Into<BigInt>) -> Self::Value {
+    fn bits_from_bigint_wrapping(self, v: BigInt) -> BitVec {
-        self.value_from_bigint_wrapping(&v.into())
+        let width = self.width();
-    }
-    fn value_from_bigint_wrapping(self, v: &BigInt) -> Self::Value;
-    fn bits_from_bigint_wrapping(self, v: &BigInt) -> BitVec {
-        let mut bits = BitVec::repeat(false, self.width());
-        Self::copy_bits_from_bigint_wrapping(v, &mut bits);
-        bits
-    }
-    fn copy_bits_from_bigint_wrapping(v: &BigInt, bits: &mut BitSlice) {
-        let width = bits.len();
         let mut bytes = v.to_signed_bytes_le();
         bytes.resize(
             width.div_ceil(u8::BITS as usize),
             if v.is_negative() { 0xFF } else { 0 },
         );
         let bitslice = &BitSlice::<u8, Lsb0>::from_slice(&bytes)[..width];
-        bits.clone_from_bitslice(bitslice);
+        let mut bits = BitVec::new();
+        bits.extend_from_bitslice(bitslice);
+        bits
     }
     fn bits_to_bigint(bits: &BitSlice) -> BigInt {
         let sign_byte = if Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false) {
@@ -631,9 +567,8 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
         BitSlice::<u8, Lsb0>::from_slice_mut(&mut bytes)[..bits.len()].clone_from_bitslice(bits);
         BigInt::from_signed_bytes_le(&bytes)
     }
-    fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value;
     fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self>;
-    fn le_bytes_to_bits_wrapping(bytes: &[u8], bit_width: usize) -> BitVec {
+    fn le_bytes_to_expr_wrapping(bytes: &[u8], bit_width: usize) -> Expr<Self> {
         let bitslice = BitSlice::<u8, Lsb0>::from_slice(bytes);
         let bitslice = &bitslice[..bit_width.min(bitslice.len())];
         let mut bits = BitVec::new();
@@ -642,17 +577,7 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
             bit_width,
             Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false),
         );
-        bits
+        Self::bits_to_expr(Cow::Owned(bits))
-    }
-    fn le_bytes_to_expr_wrapping(bytes: &[u8], bit_width: usize) -> Expr<Self> {
-        Self::bits_to_expr(Cow::Owned(Self::le_bytes_to_bits_wrapping(
-            bytes, bit_width,
-        )))
-    }
-    fn le_bytes_to_value_wrapping(bytes: &[u8], bit_width: usize) -> Self::Value {
-        Self::bits_to_value(Cow::Owned(Self::le_bytes_to_bits_wrapping(
-            bytes, bit_width,
-        )))
     }
 }
 
@@ -704,7 +629,6 @@ impl sealed::BoolOrIntTypeSealed for Bool {}
 impl BoolOrIntType for Bool {
     type Width = ConstUsize<1>;
     type Signed = ConstBool<false>;
-    type Value = bool;
 
     fn width(self) -> usize {
         1
@@ -715,19 +639,10 @@ impl BoolOrIntType for Bool {
         Bool
     }
 
-    fn value_from_bigint_wrapping(self, v: &BigInt) -> Self::Value {
-        v.bit(0)
-    }
-
     fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self> {
         assert_eq!(bits.len(), 1);
         bits[0].to_expr()
     }
-
-    fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value {
-        assert_eq!(bits.len(), 1);
-        bits[0]
-    }
 }
 
 impl Bool {
@@ -778,31 +693,3 @@ impl ToLiteralBits for bool {
         Ok(interned_bit(*self))
     }
 }
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-
-    #[test]
-    fn test_uint_for_value() {
-        assert_eq!(UInt::for_value(0u8).width, 0);
-        assert_eq!(UInt::for_value(1u8).width, 1);
-        assert_eq!(UInt::for_value(2u8).width, 2);
-        assert_eq!(UInt::for_value(3u8).width, 2);
-        assert_eq!(UInt::for_value(4u8).width, 3);
-    }
-
-    #[test]
-    fn test_sint_for_value() {
-        assert_eq!(SInt::for_value(-5).width, 4);
-        assert_eq!(SInt::for_value(-4).width, 3);
-        assert_eq!(SInt::for_value(-3).width, 3);
-        assert_eq!(SInt::for_value(-2).width, 2);
-        assert_eq!(SInt::for_value(-1).width, 1);
-        assert_eq!(SInt::for_value(0).width, 0);
-        assert_eq!(SInt::for_value(1).width, 2);
-        assert_eq!(SInt::for_value(2).width, 3);
-        assert_eq!(SInt::for_value(3).width, 3);
-        assert_eq!(SInt::for_value(4).width, 4);
-    }
-}

crates/fayalite/src/lib.rs

@@ -11,59 +11,6 @@ extern crate self as fayalite;
 #[doc(hidden)]
 pub use std as __std;
 
-#[doc(hidden)]
-#[macro_export]
-macro_rules! __cfg_expansion_helper {
-    (
-        [
-            $($evaluated_cfgs:ident($($evaluated_exprs:tt)*) = $evaluated_results:ident,)*
-        ]
-        [
-            $cfg:ident($($expr:tt)*),
-            $($unevaluated_cfgs:ident($($unevaluated_exprs:tt)*),)*
-        ]
-        // pass as tt so we get right span for attribute
-        $after_evaluation_attr:tt $after_evaluation_body:tt
-    ) => {
-        #[$cfg($($expr)*)]
-        $crate::__cfg_expansion_helper! {
-            [
-                $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
-                $cfg($($expr)*) = true,
-            ]
-            [
-                $($unevaluated_cfgs($($unevaluated_exprs)*),)*
-            ]
-            $after_evaluation_attr $after_evaluation_body
-        }
-        #[$cfg(not($($expr)*))]
-        $crate::__cfg_expansion_helper! {
-            [
-                $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
-                $cfg($($expr)*) = false,
-            ]
-            [
-                $($unevaluated_cfgs($($unevaluated_exprs)*),)*
-            ]
-            $after_evaluation_attr $after_evaluation_body
-        }
-    };
-    (
-        [
-            $($evaluated_cfgs:ident($($evaluated_exprs:tt)*) = $evaluated_results:ident,)*
-        ]
-        []
-        // don't use #[...] so we get right span for `#` and `[]` of attribute
-        {$($after_evaluation_attr:tt)*} {$($after_evaluation_body:tt)*}
-    ) => {
-        $($after_evaluation_attr)*
-        #[__evaluated_cfgs([
-            $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
-        ])]
-        $($after_evaluation_body)*
-    };
-}
-
 #[doc(inline)]
 /// The `#[hdl_module]` attribute is applied to a Rust function so that that function creates
 /// a [`Module`][`::fayalite::module::Module`] when called.
@@ -99,7 +46,6 @@ pub mod module;
 pub mod prelude;
 pub mod reg;
 pub mod reset;
-pub mod sim;
 pub mod source_location;
 pub mod testing;
 pub mod ty;

crates/fayalite/src/memory.rs

@@ -22,7 +22,7 @@ use std::{
     fmt,
     hash::{Hash, Hasher},
     marker::PhantomData,
-    num::NonZeroUsize,
+    num::NonZeroU32,
     rc::Rc,
 };
 
@@ -478,7 +478,7 @@ struct MemImpl<Element: Type, Len: Size, P> {
     initial_value: Option<Interned<BitSlice>>,
     ports: P,
     read_latency: usize,
-    write_latency: NonZeroUsize,
+    write_latency: NonZeroU32,
     read_under_write: ReadUnderWrite,
     port_annotations: Interned<[TargetedAnnotation]>,
     mem_annotations: Interned<[Annotation]>,
@@ -519,12 +519,7 @@ impl<Element: Type, Len: Size> fmt::Debug for Mem<Element, Len> {
         f.debug_struct("Mem")
             .field("name", scoped_name)
             .field("array_type", array_type)
-            .field(
+            .field("initial_value", initial_value)
-                "initial_value",
-                &initial_value.as_ref().map(|initial_value| {
-                    DebugMemoryData::from_bit_slice(*array_type, initial_value)
-                }),
-            )
             .field("read_latency", read_latency)
             .field("write_latency", write_latency)
             .field("read_under_write", read_under_write)
@@ -567,7 +562,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
         initial_value: Option<Interned<BitSlice>>,
         ports: Interned<[MemPort<DynPortType>]>,
         read_latency: usize,
-        write_latency: NonZeroUsize,
+        write_latency: NonZeroU32,
         read_under_write: ReadUnderWrite,
         port_annotations: Interned<[TargetedAnnotation]>,
         mem_annotations: Interned<[Annotation]>,
@@ -650,7 +645,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
     pub fn read_latency(self) -> usize {
         self.0.read_latency
     }
-    pub fn write_latency(self) -> NonZeroUsize {
+    pub fn write_latency(self) -> NonZeroU32 {
         self.0.write_latency
     }
     pub fn read_under_write(self) -> ReadUnderWrite {
@@ -712,7 +707,7 @@ pub(crate) struct MemBuilderTarget {
     pub(crate) initial_value: Option<Interned<BitSlice>>,
     pub(crate) ports: Vec<MemPort<DynPortType>>,
     pub(crate) read_latency: usize,
-    pub(crate) write_latency: NonZeroUsize,
+    pub(crate) write_latency: NonZeroU32,
     pub(crate) read_under_write: ReadUnderWrite,
     pub(crate) port_annotations: Vec<TargetedAnnotation>,
     pub(crate) mem_annotations: Vec<Annotation>,
@@ -872,7 +867,7 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
             initial_value: None,
             ports: vec![],
             read_latency: 0,
-            write_latency: NonZeroUsize::new(1).unwrap(),
+            write_latency: NonZeroU32::new(1).unwrap(),
             read_under_write: ReadUnderWrite::Old,
             port_annotations: vec![],
             mem_annotations: vec![],
@@ -1035,10 +1030,10 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
     pub fn read_latency(&mut self, read_latency: usize) {
         self.target.borrow_mut().read_latency = read_latency;
     }
-    pub fn get_write_latency(&self) -> NonZeroUsize {
+    pub fn get_write_latency(&self) -> NonZeroU32 {
         self.target.borrow().write_latency
     }
-    pub fn write_latency(&mut self, write_latency: NonZeroUsize) {
+    pub fn write_latency(&mut self, write_latency: NonZeroU32) {
         self.target.borrow_mut().write_latency = write_latency;
     }
     pub fn get_read_under_write(&self) -> ReadUnderWrite {
@@ -1084,61 +1079,3 @@ pub fn splat_mask<T: Type>(ty: T, value: Expr<Bool>) -> Expr<AsMask<T>> {
         )),
     }
 }
-
-pub trait DebugMemoryDataGetElement {
-    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice;
-}
-
-impl<'a, F: ?Sized + Fn(usize, Array) -> &'a BitSlice> DebugMemoryDataGetElement for &'a F {
-    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice {
-        self(element_index, array_type)
-    }
-}
-
-#[derive(Clone)]
-pub struct DebugMemoryData<GetElement: DebugMemoryDataGetElement> {
-    pub array_type: Array,
-    pub get_element: GetElement,
-}
-
-impl DebugMemoryDataGetElement for &'_ BitSlice {
-    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice {
-        assert!(element_index < array_type.len());
-        let stride = array_type.element().bit_width();
-        let start = element_index
-            .checked_mul(stride)
-            .expect("memory is too big");
-        let end = start.checked_add(stride).expect("memory is too big");
-        &self[start..end]
-    }
-}
-
-impl<'a> DebugMemoryData<&'a BitSlice> {
-    pub fn from_bit_slice<T: Type, Depth: Size>(
-        array_type: ArrayType<T, Depth>,
-        bit_slice: &'a BitSlice,
-    ) -> Self {
-        let array_type = array_type.as_dyn_array();
-        assert_eq!(bit_slice.len(), array_type.type_properties().bit_width);
-        Self {
-            array_type,
-            get_element: bit_slice,
-        }
-    }
-}
-
-impl<GetElement: DebugMemoryDataGetElement> fmt::Debug for DebugMemoryData<GetElement> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        if self.array_type.len() == 0 {
-            return f.write_str("[]");
-        }
-        writeln!(f, "[\n    // len = {:#x}", self.array_type.len())?;
-        for element_index in 0..self.array_type.len() {
-            let element = crate::util::BitSliceWriteWithBase(
-                self.get_element.get_element(element_index, self.array_type),
-            );
-            writeln!(f, "    [{element_index:#x}]: {element:#x},")?;
-        }
-        f.write_str("]")
-    }
-}

crates/fayalite/src/module.rs

@@ -20,7 +20,6 @@ use crate::{
     intern::{Intern, Interned},
     memory::{Mem, MemBuilder, MemBuilderTarget, PortName},
     reg::Reg,
-    reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     util::ScopedRef,
@@ -181,7 +180,7 @@ impl Block {
     }
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+#[derive(Clone, PartialEq, Eq, Hash)]
 pub struct StmtConnect {
     pub lhs: Expr<CanonicalType>,
     pub rhs: Expr<CanonicalType>,
@@ -236,7 +235,7 @@ impl fmt::Debug for StmtConnect {
     }
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+#[derive(Clone, PartialEq, Eq, Hash)]
 pub struct StmtFormal {
     pub kind: FormalKind,
     pub clk: Expr<Clock>,
@@ -285,8 +284,6 @@ pub struct StmtIf<S: ModuleBuildingStatus = ModuleBuilt> {
     pub blocks: [S::Block; 2],
 }
 
-impl Copy for StmtIf {}
-
 impl<S: ModuleBuildingStatus> StmtIf<S> {
     pub fn then_block(&self) -> S::Block {
         self.blocks[0]
@@ -318,8 +315,6 @@ pub struct StmtMatch<S: ModuleBuildingStatus = ModuleBuilt> {
     pub blocks: Interned<[S::Block]>,
 }
 
-impl Copy for StmtMatch {}
-
 impl StmtMatch {
     #[track_caller]
     fn assert_validity(&self) {
@@ -351,7 +346,7 @@ macro_rules! wrapper_enum {
         $(#[$enum_meta:meta])*
         $vis:vis enum $enum_name:ident<$T_enum:ident: $T_bound:ident = $T_enum_default:ident> {
             $(
-                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident $(, from = $from:ident)?]
+                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident]
                 $(#[$variant_meta:meta])*
                 $Variant:ident($VariantTy:ty),
             )*
@@ -363,7 +358,7 @@ macro_rules! wrapper_enum {
             $(#[$enum_meta])*
             $vis enum $enum_name<$T_enum: $T_bound = $T_enum_default> {
                 $(
-                    #[is = $is_fn, as_ref = $as_ref_fn $(, from = $from)?]
+                    #[is = $is_fn, as_ref = $as_ref_fn]
                     $(#[$variant_meta])*
                     $Variant($VariantTy),
                 )*
@@ -390,7 +385,7 @@ macro_rules! wrapper_enum {
         $(#[$enum_meta:meta])*
         $vis:vis enum $enum_name:ident<$T_enum:ident: $T_bound:ident = $T_enum_default:ident> {
             $(
-                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident $(, from = $from:ident)?]
+                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident]
                 $(#[$variant_meta:meta])*
                 $Variant:ident($VariantTy:ty),
             )*
@@ -402,22 +397,22 @@ macro_rules! wrapper_enum {
             $(#[$enum_meta])*
             $vis enum $enum_name<$T_enum: $T_bound = $T_enum_default> {
                 $(
-                    #[is = $is_fn, as_ref = $as_ref_fn $(, from = $from)?]
+                    #[is = $is_fn, as_ref = $as_ref_fn]
                     $(#[$variant_meta])*
                     $Variant($VariantTy),
                 )*
             }
         }
 
-        $($(
+        $(
             wrapper_enum! {
                 impl $T_to From<$VariantTy> for $to_type {
-                    fn $from(value: $VariantTy) -> Self {
+                    fn from(value: $VariantTy) -> Self {
                         $enum_name::$Variant(value).into()
                     }
                 }
             }
-        )?)*
+        )*
     };
     (
         #[impl()]
@@ -425,7 +420,7 @@ macro_rules! wrapper_enum {
         $(#[$enum_meta:meta])*
         $vis:vis enum $enum_name:ident<$T_enum:ident: $T_bound:ident = $T_enum_default:ident> {
             $(
-                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident $(, from = $from:ident)?]
+                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident]
                 $(#[$variant_meta:meta])*
                 $Variant:ident($VariantTy:ty),
             )*
@@ -464,15 +459,13 @@ pub struct StmtWire<S: ModuleBuildingStatus = ModuleBuilt> {
     pub wire: Wire<CanonicalType>,
 }
 
-impl Copy for StmtWire {}
-
 #[derive(Hash, Clone, PartialEq, Eq, Debug)]
-pub struct StmtReg<R: ResetType, S: ModuleBuildingStatus = ModuleBuilt> {
+pub struct StmtReg<S: ModuleBuildingStatus = ModuleBuilt> {
     pub annotations: S::StmtAnnotations,
-    pub reg: Reg<CanonicalType, R>,
+    pub reg: Reg<CanonicalType>,
 }
 
-impl<R: ResetType> Copy for StmtReg<R> {}
+impl Copy for StmtReg {}
 
 #[derive(Clone, PartialEq, Eq, Hash, Debug)]
 pub struct StmtInstance<S: ModuleBuildingStatus = ModuleBuilt> {
@@ -480,8 +473,6 @@ pub struct StmtInstance<S: ModuleBuildingStatus = ModuleBuilt> {
     pub instance: Instance<Bundle>,
 }
 
-impl Copy for StmtInstance {}
-
 wrapper_enum! {
     #[impl(
         (<S: ModuleBuildingStatus>) self: StmtDeclaration<S> = self,
@@ -490,57 +481,20 @@ wrapper_enum! {
     #[to((<S: ModuleBuildingStatus>) StmtDeclaration<S>, (<S: ModuleBuildingStatus>) Stmt<S>)]
     #[derive(Clone, PartialEq, Eq, Hash)]
     pub enum StmtDeclaration<S: ModuleBuildingStatus = ModuleBuilt> {
-        #[is = is_wire, as_ref = wire, from = from]
+        #[is = is_wire, as_ref = wire]
         Wire(StmtWire<S>),
         #[is = is_reg, as_ref = reg]
-        Reg(StmtReg<Reset, S>),
+        Reg(StmtReg<S>),
-        #[is = is_reg_sync, as_ref = reg_sync]
+        #[is = is_instance, as_ref = instance]
-        RegSync(StmtReg<SyncReset, S>),
-        #[is = is_reg_async, as_ref = reg_async]
-        RegAsync(StmtReg<AsyncReset, S>),
-        #[is = is_instance, as_ref = instance, from = from]
         Instance(StmtInstance<S>),
     }
 }
 
-impl Copy for StmtDeclaration {}
-
-impl<S: ModuleBuildingStatus, R: ResetType> From<StmtReg<R, S>> for Stmt<S> {
-    fn from(value: StmtReg<R, S>) -> Self {
-        StmtDeclaration::from(value).into()
-    }
-}
-
-impl<S: ModuleBuildingStatus, R: ResetType> From<StmtReg<R, S>> for StmtDeclaration<S> {
-    fn from(value: StmtReg<R, S>) -> Self {
-        struct Dispatch<S>(PhantomData<S>);
-        impl<S: ModuleBuildingStatus> ResetTypeDispatch for Dispatch<S> {
-            type Input<T: ResetType> = StmtReg<T, S>;
-            type Output<T: ResetType> = StmtDeclaration<S>;
-
-            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
-                StmtDeclaration::Reg(input)
-            }
-
-            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
-                StmtDeclaration::RegSync(input)
-            }
-
-            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
-                StmtDeclaration::RegAsync(input)
-            }
-        }
-        R::dispatch(value, Dispatch(PhantomData))
-    }
-}
-
 impl<S: ModuleBuildingStatus> StmtDeclaration<S> {
     pub fn annotations(&self) -> S::StmtAnnotations {
         match self {
             StmtDeclaration::Wire(v) => v.annotations,
             StmtDeclaration::Reg(v) => v.annotations,
-            StmtDeclaration::RegSync(v) => v.annotations,
-            StmtDeclaration::RegAsync(v) => v.annotations,
             StmtDeclaration::Instance(v) => v.annotations,
         }
     }
@@ -548,8 +502,6 @@ impl<S: ModuleBuildingStatus> StmtDeclaration<S> {
         match self {
             StmtDeclaration::Wire(v) => v.wire.source_location(),
             StmtDeclaration::Reg(v) => v.reg.source_location(),
-            StmtDeclaration::RegSync(v) => v.reg.source_location(),
-            StmtDeclaration::RegAsync(v) => v.reg.source_location(),
             StmtDeclaration::Instance(v) => v.instance.source_location(),
         }
     }
@@ -557,26 +509,20 @@ impl<S: ModuleBuildingStatus> StmtDeclaration<S> {
         match self {
             StmtDeclaration::Wire(v) => v.wire.scoped_name(),
             StmtDeclaration::Reg(v) => v.reg.scoped_name(),
-            StmtDeclaration::RegSync(v) => v.reg.scoped_name(),
-            StmtDeclaration::RegAsync(v) => v.reg.scoped_name(),
             StmtDeclaration::Instance(v) => v.instance.scoped_name(),
         }
     }
     pub fn sub_stmt_blocks(&self) -> &[S::Block] {
         match self {
-            StmtDeclaration::Wire(_)
+            StmtDeclaration::Wire(_) | StmtDeclaration::Reg(_) | StmtDeclaration::Instance(_) => {
-            | StmtDeclaration::Reg(_)
+                &[]
-            | StmtDeclaration::RegSync(_)
+            }
-            | StmtDeclaration::RegAsync(_)
-            | StmtDeclaration::Instance(_) => &[],
         }
     }
     pub fn canonical_ty(&self) -> CanonicalType {
         match self {
             StmtDeclaration::Wire(v) => v.wire.ty(),
             StmtDeclaration::Reg(v) => v.reg.ty(),
-            StmtDeclaration::RegSync(v) => v.reg.ty(),
-            StmtDeclaration::RegAsync(v) => v.reg.ty(),
             StmtDeclaration::Instance(v) => CanonicalType::Bundle(v.instance.ty()),
         }
     }
@@ -587,21 +533,19 @@ wrapper_enum! {
     #[to((<S: ModuleBuildingStatus>) Stmt<S>)]
     #[derive(Clone, PartialEq, Eq, Hash)]
     pub enum Stmt<S: ModuleBuildingStatus = ModuleBuilt> {
-        #[is = is_connect, as_ref = connect, from = from]
+        #[is = is_connect, as_ref = connect]
         Connect(StmtConnect),
-        #[is = is_formal, as_ref = formal, from = from]
+        #[is = is_formal, as_ref = formal]
         Formal(StmtFormal),
-        #[is = is_if, as_ref = if_, from = from]
+        #[is = is_if, as_ref = if_]
         If(StmtIf<S>),
-        #[is = is_match, as_ref = match_, from = from]
+        #[is = is_match, as_ref = match_]
         Match(StmtMatch<S>),
-        #[is = is_declaration, as_ref = declaration, from = from]
+        #[is = is_declaration, as_ref = declaration]
         Declaration(StmtDeclaration<S>),
     }
 }
 
-impl Copy for Stmt {}
-
 impl<S: ModuleBuildingStatus> Stmt<S> {
     pub fn sub_stmt_blocks(&self) -> &[S::Block] {
         match self {
@@ -770,18 +714,6 @@ impl<T: BundleType> Instance<T> {
             source_location,
         }
     }
-    pub fn from_canonical(v: Instance<Bundle>) -> Self {
-        let Instance {
-            scoped_name,
-            instantiated,
-            source_location,
-        } = v;
-        Self {
-            scoped_name,
-            instantiated: Module::from_canonical(*instantiated).intern_sized(),
-            source_location,
-        }
-    }
     pub fn containing_module_name(self) -> Interned<str> {
         self.containing_module_name_id().0
     }
@@ -1026,14 +958,6 @@ impl From<NormalModuleBody<ModuleBuilding>> for NormalModuleBody {
                                 annotations: (),
                                 reg,
                             }) => StmtReg { annotations, reg }.into(),
-                            StmtDeclaration::RegSync(StmtReg {
-                                annotations: (),
-                                reg,
-                            }) => StmtReg { annotations, reg }.into(),
-                            StmtDeclaration::RegAsync(StmtReg {
-                                annotations: (),
-                                reg,
-                            }) => StmtReg { annotations, reg }.into(),
                             StmtDeclaration::Instance(StmtInstance {
                                 annotations: (),
                                 instance,
@@ -1737,14 +1661,6 @@ impl AssertValidityState {
                     annotations: _,
                     reg,
                 })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
-                Stmt::Declaration(StmtDeclaration::RegSync(StmtReg {
-                    annotations: _,
-                    reg,
-                })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
-                Stmt::Declaration(StmtDeclaration::RegAsync(StmtReg {
-                    annotations: _,
-                    reg,
-                })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
                 Stmt::Declaration(StmtDeclaration::Instance(StmtInstance {
                     annotations: _,
                     instance,
@@ -1926,10 +1842,10 @@ impl<CD> RegBuilder<CD, (), ()> {
 }
 
 impl<I, T: Type> RegBuilder<(), I, T> {
-    pub fn clock_domain<R: ResetType>(
+    pub fn clock_domain(
         self,
-        clock_domain: impl ToExpr<Type = ClockDomain<R>>,
+        clock_domain: impl ToExpr<Type = ClockDomain>,
-    ) -> RegBuilder<Expr<ClockDomain<R>>, I, T> {
+    ) -> RegBuilder<Expr<ClockDomain>, I, T> {
         let Self {
             name,
             source_location,
@@ -1947,7 +1863,7 @@ impl<I, T: Type> RegBuilder<(), I, T> {
     }
 }
 
-impl<T: Type, R: ResetType> RegBuilder<Expr<ClockDomain<R>>, Option<Expr<T>>, T> {
+impl<T: Type> RegBuilder<Expr<ClockDomain>, Option<Expr<T>>, T> {
     #[track_caller]
     pub fn build(self) -> Expr<T> {
         let Self {
@@ -2272,16 +2188,6 @@ pub fn annotate<T: Type>(target: Expr<T>, annotations: impl IntoAnnotations) {
             reg,
         }
         .into(),
-        TargetBase::RegSync(reg) => StmtReg {
-            annotations: (),
-            reg,
-        }
-        .into(),
-        TargetBase::RegAsync(reg) => StmtReg {
-            annotations: (),
-            reg,
-        }
-        .into(),
         TargetBase::Wire(wire) => StmtWire {
             annotations: (),
             wire,
@@ -2723,50 +2629,3 @@ impl<T: Type> ModuleIO<T> {
         self.ty
     }
 }
-
-#[derive(PartialEq, Eq, Hash, Clone, Copy)]
-pub enum InstantiatedModule {
-    Base(Interned<Module<Bundle>>),
-    Child {
-        parent: Interned<InstantiatedModule>,
-        instance: Interned<Instance<Bundle>>,
-    },
-}
-
-impl InstantiatedModule {
-    pub fn leaf_module(self) -> Interned<Module<Bundle>> {
-        match self {
-            InstantiatedModule::Base(base) => base,
-            InstantiatedModule::Child { instance, .. } => instance.instantiated(),
-        }
-    }
-    fn write_path(self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        match self {
-            InstantiatedModule::Base(base) => fmt::Debug::fmt(&base.name_id(), f),
-            InstantiatedModule::Child { parent, instance } => {
-                parent.write_path(f)?;
-                write!(f, ".{}", instance.name_id())
-            }
-        }
-    }
-}
-
-impl fmt::Debug for InstantiatedModule {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        write!(f, "InstantiatedModule(")?;
-        self.write_path(f)?;
-        write!(f, ": {})", self.leaf_module().name_id())
-    }
-}
-
-#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
-pub struct TargetInInstantiatedModule {
-    pub instantiated_module: InstantiatedModule,
-    pub target: Target,
-}
-
-#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
-pub struct ExprInInstantiatedModule<T: Type> {
-    pub instantiated_module: InstantiatedModule,
-    pub expr: Expr<T>,
-}

crates/fayalite/src/module/transform.rs

@@ -1,6 +1,5 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-pub mod deduce_resets;
 pub mod simplify_enums;
 pub mod simplify_memories;
 pub mod visit;

crates/fayalite/src/module/transform/simplify_enums.rs

@@ -764,9 +764,7 @@ impl Folder for State {
             | ExprEnum::ModuleIO(_)
             | ExprEnum::Instance(_)
             | ExprEnum::Wire(_)
-            | ExprEnum::Reg(_)
+            | ExprEnum::Reg(_) => op.default_fold(self),
-            | ExprEnum::RegSync(_)
-            | ExprEnum::RegAsync(_) => op.default_fold(self),
         }
     }
 

crates/fayalite/src/module/transform/visit.rs

@@ -29,7 +29,7 @@ use crate::{
         StmtInstance, StmtMatch, StmtReg, StmtWire,
     },
     reg::Reg,
-    reset::{AsyncReset, Reset, ResetType, SyncReset},
+    reset::{AsyncReset, Reset, SyncReset},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     wire::Wire,

crates/fayalite/src/reg.rs

@@ -5,22 +5,21 @@ use crate::{
     expr::{Expr, Flow},
     intern::Interned,
     module::{NameId, ScopedNameId},
-    reset::{Reset, ResetType},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
 };
 use std::fmt;
 
 #[derive(Copy, Clone, Eq, PartialEq, Hash)]
-pub struct Reg<T: Type, R: ResetType = Reset> {
+pub struct Reg<T: Type> {
     name: ScopedNameId,
     source_location: SourceLocation,
     ty: T,
-    clock_domain: Expr<ClockDomain<R>>,
+    clock_domain: Expr<ClockDomain>,
     init: Option<Expr<T>>,
 }
 
-impl<T: Type + fmt::Debug, R: ResetType> fmt::Debug for Reg<T, R> {
+impl<T: Type + fmt::Debug> fmt::Debug for Reg<T> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
             name,
@@ -38,8 +37,8 @@ impl<T: Type + fmt::Debug, R: ResetType> fmt::Debug for Reg<T, R> {
     }
 }
 
-impl<T: Type, R: ResetType> Reg<T, R> {
+impl<T: Type> Reg<T> {
-    pub fn canonical(&self) -> Reg<CanonicalType, R> {
+    pub fn canonical(&self) -> Reg<CanonicalType> {
         let Self {
             name,
             source_location,
@@ -60,7 +59,7 @@ impl<T: Type, R: ResetType> Reg<T, R> {
         scoped_name: ScopedNameId,
         source_location: SourceLocation,
         ty: T,
-        clock_domain: Expr<ClockDomain<R>>,
+        clock_domain: Expr<ClockDomain>,
         init: Option<Expr<T>>,
     ) -> Self {
         assert!(
@@ -99,7 +98,7 @@ impl<T: Type, R: ResetType> Reg<T, R> {
     pub fn scoped_name(&self) -> ScopedNameId {
         self.name
     }
-    pub fn clock_domain(&self) -> Expr<ClockDomain<R>> {
+    pub fn clock_domain(&self) -> Expr<ClockDomain> {
         self.clock_domain
     }
     pub fn init(&self) -> Option<Expr<T>> {

crates/fayalite/src/reset.rs

@@ -1,9 +1,8 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use crate::{
-    clock::Clock,
+    expr::{Expr, ToExpr},
-    expr::{ops, Expr, ToExpr},
+    int::Bool,
-    int::{Bool, SInt, UInt},
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
 };
@@ -12,33 +11,10 @@ mod sealed {
     pub trait ResetTypeSealed {}
 }
 
-pub trait ResetType:
+pub trait ResetType: StaticType<MaskType = Bool> + sealed::ResetTypeSealed {}
-    StaticType<MaskType = Bool>
-    + sealed::ResetTypeSealed
-    + ops::ExprCastTo<Bool>
-    + ops::ExprCastTo<Reset>
-    + ops::ExprCastTo<SyncReset>
-    + ops::ExprCastTo<AsyncReset>
-    + ops::ExprCastTo<Clock>
-    + ops::ExprCastTo<UInt<1>>
-    + ops::ExprCastTo<SInt<1>>
-    + ops::ExprCastTo<UInt>
-    + ops::ExprCastTo<SInt>
-{
-    fn dispatch<D: ResetTypeDispatch>(input: D::Input<Self>, dispatch: D) -> D::Output<Self>;
-}
-
-pub trait ResetTypeDispatch: Sized {
-    type Input<T: ResetType>;
-    type Output<T: ResetType>;
-
-    fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset>;
-    fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset>;
-    fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset>;
-}
 
 macro_rules! reset_type {
-    ($name:ident, $(#[$impl_trait:ident])? $Trait:ident::$trait_fn:ident, $is_castable_from_bits:literal, $dispatch_fn:ident) => {
+    ($name:ident, $Trait:ident::$trait_fn:ident, $is_castable_from_bits:literal) => {
         #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)]
         pub struct $name;
 
@@ -91,14 +67,7 @@ macro_rules! reset_type {
 
         impl sealed::ResetTypeSealed for $name {}
 
-        impl ResetType for $name {
+        impl ResetType for $name {}
-            fn dispatch<D: ResetTypeDispatch>(
-                input: D::Input<Self>,
-                dispatch: D,
-            ) -> D::Output<Self> {
-                dispatch.$dispatch_fn(input)
-            }
-        }
 
         pub trait $Trait {
             fn $trait_fn(&self) -> Expr<$name>;
@@ -122,21 +91,20 @@ macro_rules! reset_type {
             }
         }
 
-        $($impl_trait $Trait for Expr<$name> {
+        impl $Trait for Expr<$name> {
             fn $trait_fn(&self) -> Expr<$name> {
                 *self
             }
-        })?
+        }
     };
 }
 
-reset_type!(AsyncReset, #[impl] ToAsyncReset::to_async_reset, true, async_reset);
+reset_type!(AsyncReset, ToAsyncReset::to_async_reset, true);
-reset_type!(SyncReset, #[impl] ToSyncReset::to_sync_reset, true, sync_reset);
+reset_type!(SyncReset, ToSyncReset::to_sync_reset, true);
 reset_type!(
     Reset,
     ToReset::to_reset,
-    false, // Reset is not castable from bits because we don't know if it's async or sync
+    false // Reset is not castable from bits because we don't know if it's async or sync
-    reset
 );
 
 impl ToSyncReset for bool {

crates/fayalite/src/sim/time.rs

@@ -1,397 +0,0 @@
-// SPDX-License-Identifier: LGPL-3.0-or-later
-// See Notices.txt for copyright information
-use std::{
-    fmt,
-    ops::{Add, AddAssign, Sub, SubAssign},
-    time::Duration,
-};
-
-#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
-pub struct SimInstant {
-    time_since_start: SimDuration,
-}
-
-impl SimInstant {
-    pub const fn checked_add(self, duration: SimDuration) -> Option<Self> {
-        let Some(time_since_start) = self.time_since_start.checked_add(duration) else {
-            return None;
-        };
-        Some(SimInstant { time_since_start })
-    }
-    pub const fn checked_duration_since(self, earlier: Self) -> Option<SimDuration> {
-        self.time_since_start.checked_sub(earlier.time_since_start)
-    }
-    pub const fn checked_sub(self, duration: SimDuration) -> Option<Self> {
-        let Some(time_since_start) = self.time_since_start.checked_sub(duration) else {
-            return None;
-        };
-        Some(SimInstant { time_since_start })
-    }
-    #[track_caller]
-    pub const fn duration_since(self, earlier: Self) -> SimDuration {
-        let Some(retval) = self.checked_duration_since(earlier) else {
-            panic!(
-                "tried to compute the duration since a later time -- durations can't be negative"
-            );
-        };
-        retval
-    }
-    pub const fn saturating_duration_since(self, earlier: Self) -> SimDuration {
-        let Some(retval) = self.checked_duration_since(earlier) else {
-            return SimDuration::ZERO;
-        };
-        retval
-    }
-}
-
-impl Add<SimDuration> for SimInstant {
-    type Output = SimInstant;
-
-    #[track_caller]
-    fn add(mut self, rhs: SimDuration) -> Self::Output {
-        self += rhs;
-        self
-    }
-}
-
-impl AddAssign<SimDuration> for SimInstant {
-    #[track_caller]
-    fn add_assign(&mut self, rhs: SimDuration) {
-        self.time_since_start += rhs;
-    }
-}
-
-impl Add<SimInstant> for SimDuration {
-    type Output = SimInstant;
-
-    #[track_caller]
-    fn add(self, rhs: SimInstant) -> Self::Output {
-        rhs.add(self)
-    }
-}
-
-impl Sub for SimInstant {
-    type Output = SimDuration;
-
-    #[track_caller]
-    fn sub(self, rhs: SimInstant) -> Self::Output {
-        self.duration_since(rhs)
-    }
-}
-
-impl Sub<SimDuration> for SimInstant {
-    type Output = SimInstant;
-
-    #[track_caller]
-    fn sub(self, rhs: SimDuration) -> Self::Output {
-        let Some(retval) = self.checked_sub(rhs) else {
-            panic!("SimInstant underflow");
-        };
-        retval
-    }
-}
-
-impl SubAssign<SimDuration> for SimInstant {
-    #[track_caller]
-    fn sub_assign(&mut self, rhs: SimDuration) {
-        *self = *self - rhs;
-    }
-}
-
-impl SimInstant {
-    pub const START: SimInstant = SimInstant {
-        time_since_start: SimDuration::ZERO,
-    };
-}
-
-impl fmt::Debug for SimInstant {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.time_since_start.fmt(f)
-    }
-}
-
-#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
-pub struct SimDuration {
-    attos: u128,
-}
-
-impl AddAssign for SimDuration {
-    #[track_caller]
-    fn add_assign(&mut self, rhs: SimDuration) {
-        *self = *self + rhs;
-    }
-}
-
-impl Add for SimDuration {
-    type Output = SimDuration;
-
-    #[track_caller]
-    fn add(self, rhs: SimDuration) -> Self::Output {
-        SimDuration {
-            attos: self
-                .attos
-                .checked_add(rhs.attos)
-                .expect("overflow adding durations"),
-        }
-    }
-}
-
-impl Sub for SimDuration {
-    type Output = Self;
-
-    #[track_caller]
-    fn sub(self, rhs: Self) -> Self::Output {
-        SimDuration {
-            attos: self
-                .attos
-                .checked_add(rhs.attos)
-                .expect("underflow subtracting durations -- durations can't be negative"),
-        }
-    }
-}
-
-impl SubAssign for SimDuration {
-    #[track_caller]
-    fn sub_assign(&mut self, rhs: Self) {
-        *self = *self - rhs;
-    }
-}
-
-#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)]
-pub struct SimDurationParts {
-    pub attos: u16,
-    pub femtos: u16,
-    pub picos: u16,
-    pub nanos: u16,
-    pub micros: u16,
-    pub millis: u16,
-    pub secs: u128,
-}
-
-macro_rules! impl_duration_units {
-    (
-        $(
-            #[unit_const = $UNIT:ident, from_units = $from_units:ident, as_units = $as_units:ident, units = $units:ident, suffix = $suffix:literal]
-            const $log10_units_per_sec:ident: u32 = $log10_units_per_sec_value:expr;
-        )*
-    ) => {
-        impl SimDuration {
-            $(
-                const $log10_units_per_sec: u32 = $log10_units_per_sec_value;
-                pub const fn $from_units($units: u128) -> Self {
-                    Self::from_units_helper::<{ Self::$log10_units_per_sec }>($units)
-                }
-                pub const fn $as_units(self) -> u128 {
-                    self.attos / const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) }
-                }
-            )*
-            pub const fn to_parts(mut self) -> SimDurationParts {
-                $(
-                    let $units = self.attos / const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
-                    self.attos %= const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
-                )*
-                SimDurationParts {
-                    $($units: $units as _,)*
-                }
-            }
-            pub const fn from_parts_checked(parts: SimDurationParts) -> Option<Self> {
-                let attos = 0u128;
-                $(
-                    let Some(product) = const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) }.checked_mul(parts.$units as u128) else {
-                        return None;
-                    };
-                    let Some(attos) = attos.checked_add(product) else {
-                        return None;
-                    };
-                )*
-                Some(Self {
-                    attos,
-                })
-            }
-        }
-
-        impl fmt::Debug for SimDuration {
-            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-                let ilog10_attos = match self.attos.checked_ilog10() {
-                    Some(v) => v,
-                    None => Self::LOG10_ATTOS_PER_SEC,
-                };
-                let (suffix, int, fraction, fraction_digits) =
-                    match Self::LOG10_ATTOS_PER_SEC.saturating_sub(ilog10_attos) {
-                    $(
-                        ..=Self::$log10_units_per_sec => {
-                            let divisor = const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
-                            (
-                                $suffix,
-                                self.attos / divisor,
-                                self.attos % divisor,
-                                (Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) as usize,
-                            )
-                        },
-                    )*
-                    _ => unreachable!(),
-                };
-                write!(f, "{int}")?;
-                if fraction != 0 {
-                    write!(f, ".{fraction:0fraction_digits$}")?;
-                }
-                write!(f, " {suffix}")
-            }
-        }
-
-        #[cfg(test)]
-        #[test]
-        fn test_duration_debug() {
-            $(
-                assert_eq!(
-                    format!("{:?}", SimDuration::$from_units(123)),
-                    concat!("123 ", $suffix)
-                );
-                assert_eq!(
-                    format!("{:?}", SimDuration::$from_units(1)),
-                    concat!("1 ", $suffix),
-                );
-                let mut v = SimDuration::$from_units(1);
-                if v.attos < 1 << 53 {
-                    v.attos += 1;
-                    assert_eq!(
-                        format!("{v:?}"),
-                        format!("{} {}", v.attos as f64 / 10.0f64.powf((SimDuration::LOG10_ATTOS_PER_SEC - SimDuration::$log10_units_per_sec) as f64), $suffix),
-                        "1 {} + 1 as == {} as", $suffix, v.attos,
-                    );
-                }
-            )*
-        }
-    };
-}
-
-impl_duration_units! {
-    #[unit_const = SECOND, from_units = from_secs, as_units = as_secs, units = secs, suffix = "s"]
-    const LOG10_SECS_PER_SEC: u32 = 0;
-    #[unit_const = MILLISECOND, from_units = from_millis, as_units = as_millis, units = millis, suffix = "ms"]
-    const LOG10_MILLIS_PER_SEC: u32 = 3;
-    #[unit_const = MICROSECOND, from_units = from_micros, as_units = as_micros, units = micros, suffix = "μs"]
-    const LOG10_MICROS_PER_SEC: u32 = 6;
-    #[unit_const = NANOSECOND, from_units = from_nanos, as_units = as_nanos, units = nanos, suffix = "ns"]
-    const LOG10_NANOS_PER_SEC: u32 = 9;
-    #[unit_const = PICOSECOND, from_units = from_picos, as_units = as_picos, units = picos, suffix = "ps"]
-    const LOG10_PICOS_PER_SEC: u32 = 12;
-    #[unit_const = FEMTOSECOND, from_units = from_femtos, as_units = as_femtos, units = femtos, suffix = "fs"]
-    const LOG10_FEMTOS_PER_SEC: u32 = 15;
-    #[unit_const = ATTOSECOND, from_units = from_attos, as_units = as_attos, units = attos, suffix = "as"]
-    const LOG10_ATTOS_PER_SEC: u32 = 18;
-}
-
-impl SimDuration {
-    const fn from_units_helper<const UNITS_PER_SEC: u32>(units: u128) -> Self {
-        let Some(attos) =
-            units.checked_mul(const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - UNITS_PER_SEC) })
-        else {
-            panic!("duration too big");
-        };
-        Self { attos }
-    }
-    pub const ZERO: SimDuration = SimDuration::from_secs(0);
-    pub const fn from_parts(parts: SimDurationParts) -> Self {
-        match Self::from_parts_checked(parts) {
-            Some(v) => v,
-            None => panic!("duration too big"),
-        }
-    }
-    pub const fn abs_diff(self, other: Self) -> Self {
-        Self {
-            attos: self.attos.abs_diff(other.attos),
-        }
-    }
-    pub const fn checked_add(self, rhs: Self) -> Option<Self> {
-        let Some(attos) = self.attos.checked_add(rhs.attos) else {
-            return None;
-        };
-        Some(Self { attos })
-    }
-    pub const fn checked_sub(self, rhs: Self) -> Option<Self> {
-        let Some(attos) = self.attos.checked_sub(rhs.attos) else {
-            return None;
-        };
-        Some(Self { attos })
-    }
-    pub const fn is_zero(self) -> bool {
-        self.attos == 0
-    }
-    pub const fn saturating_add(self, rhs: Self) -> Self {
-        Self {
-            attos: self.attos.saturating_add(rhs.attos),
-        }
-    }
-    pub const fn saturating_sub(self, rhs: Self) -> Self {
-        Self {
-            attos: self.attos.saturating_sub(rhs.attos),
-        }
-    }
-    pub const fn checked_ilog10(self) -> Option<i32> {
-        let Some(ilog10_attos) = self.attos.checked_ilog10() else {
-            return None;
-        };
-        Some(ilog10_attos as i32 - Self::LOG10_ATTOS_PER_SEC as i32)
-    }
-    #[track_caller]
-    pub const fn ilog10(self) -> i32 {
-        let Some(retval) = self.checked_ilog10() else {
-            panic!("tried to take the ilog10 of 0");
-        };
-        retval
-    }
-    pub const fn checked_pow10(log10: i32, underflow_is_zero: bool) -> Option<Self> {
-        let Some(log10) = Self::LOG10_ATTOS_PER_SEC.checked_add_signed(log10) else {
-            return if log10 < 0 && underflow_is_zero {
-                Some(Self::ZERO)
-            } else {
-                None
-            };
-        };
-        let Some(attos) = 10u128.checked_pow(log10) else {
-            return None;
-        };
-        Some(Self { attos })
-    }
-    #[track_caller]
-    pub const fn pow10(log10: i32) -> Self {
-        let Some(retval) = Self::checked_pow10(log10, true) else {
-            panic!("pow10 overflowed");
-        };
-        retval
-    }
-    pub const fn is_power_of_ten(self) -> bool {
-        const TEN: u128 = 10;
-        const NUMBER_OF_POWERS_OF_TEN: usize = {
-            let mut n = 0;
-            while let Some(_) = TEN.checked_pow(n as u32) {
-                n += 1;
-            }
-            n
-        };
-        const POWERS_OF_TEN: [u128; NUMBER_OF_POWERS_OF_TEN] = {
-            let mut retval = [0; NUMBER_OF_POWERS_OF_TEN];
-            let mut i = 0;
-            while i < NUMBER_OF_POWERS_OF_TEN {
-                retval[i] = TEN.pow(i as u32);
-                i += 1;
-            }
-            retval
-        };
-        let mut i = 0;
-        while i < NUMBER_OF_POWERS_OF_TEN {
-            if self.attos == POWERS_OF_TEN[i] {
-                return true;
-            }
-            i += 1;
-        }
-        false
-    }
-}
-
-impl From<Duration> for SimDuration {
-    fn from(duration: Duration) -> Self {
-        Self::from_nanos(duration.as_nanos())
-    }
-}

crates/fayalite/src/sim/vcd.rs

@@ -1,948 +0,0 @@
-// SPDX-License-Identifier: LGPL-3.0-or-later
-// See Notices.txt for copyright information
-
-use crate::{
-    enum_::{Enum, EnumType},
-    expr::Flow,
-    int::UInt,
-    sim::{
-        time::{SimDuration, SimInstant},
-        TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl,
-        TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance,
-        TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation, TraceModule,
-        TraceModuleIO, TraceReg, TraceSInt, TraceScalar, TraceScalarId, TraceScope, TraceSyncReset,
-        TraceUInt, TraceWire, TraceWriter, TraceWriterDecls,
-    },
-};
-use bitvec::{order::Lsb0, slice::BitSlice};
-use std::{
-    fmt,
-    io::{self, Write},
-    mem,
-};
-
-pub struct VcdWriterDecls<W: io::Write + 'static> {
-    writer: W,
-    timescale: SimDuration,
-}
-
-impl<W: io::Write + 'static> VcdWriterDecls<W> {
-    pub fn new(writer: W) -> Self {
-        Self {
-            writer,
-            timescale: SimDuration::from_picos(1),
-        }
-    }
-    pub fn timescale(&self) -> SimDuration {
-        self.timescale
-    }
-    #[track_caller]
-    pub fn with_timescale(mut self, timescale: SimDuration) -> Self {
-        // check timescale validity
-        vcd_timescale(timescale);
-        self.timescale = timescale;
-        self
-    }
-}
-
-#[track_caller]
-const fn vcd_timescale(timescale: SimDuration) -> &'static str {
-    if !timescale.is_power_of_ten() {
-        panic!("VCD timescale must be a power of 10");
-    }
-    macro_rules! timescales {
-        ($($const_name:ident = ($dur:expr, $text:literal),)*) => {
-            $(const $const_name: SimDuration = $dur;)*
-            match timescale {
-                $($const_name => $text,)*
-                _ => panic!("VCD timescale is too big"),
-            }
-        };
-    }
-    timescales! {
-        TIMESCALE_1_AS = (SimDuration::from_attos(1), "1 as"),
-        TIMESCALE_10_AS = (SimDuration::from_attos(10), "10 as"),
-        TIMESCALE_100_AS = (SimDuration::from_attos(100), "100 as"),
-        TIMESCALE_1_FS = (SimDuration::from_femtos(1), "1 fs"),
-        TIMESCALE_10_FS = (SimDuration::from_femtos(10), "10 fs"),
-        TIMESCALE_100_FS = (SimDuration::from_femtos(100), "100 fs"),
-        TIMESCALE_1_PS = (SimDuration::from_picos(1), "1 ps"),
-        TIMESCALE_10_PS = (SimDuration::from_picos(10), "10 ps"),
-        TIMESCALE_100_PS = (SimDuration::from_picos(100), "100 ps"),
-        TIMESCALE_1_NS = (SimDuration::from_nanos(1), "1 ns"),
-        TIMESCALE_10_NS = (SimDuration::from_nanos(10), "10 ns"),
-        TIMESCALE_100_NS = (SimDuration::from_nanos(100), "100 ns"),
-        TIMESCALE_1_US = (SimDuration::from_micros(1), "1 us"),
-        TIMESCALE_10_US = (SimDuration::from_micros(10), "10 us"),
-        TIMESCALE_100_US = (SimDuration::from_micros(100), "100 us"),
-        TIMESCALE_1_MS = (SimDuration::from_millis(1), "1 ms"),
-        TIMESCALE_10_MS = (SimDuration::from_millis(10), "10 ms"),
-        TIMESCALE_100_MS = (SimDuration::from_millis(100), "100 ms"),
-        TIMESCALE_1_S = (SimDuration::from_secs(1), "1 s"),
-        TIMESCALE_10_S = (SimDuration::from_secs(10), "10 s"),
-        TIMESCALE_100_S = (SimDuration::from_secs(100), "100 s"),
-        TIMESCALE_1000_S = (SimDuration::from_secs(1000), "1000 s"),
-    }
-}
-
-impl<W: io::Write> fmt::Debug for VcdWriterDecls<W> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let Self {
-            writer: _,
-            timescale,
-        } = self;
-        f.debug_struct("VcdWriterDecls")
-            .field("timescale", timescale)
-            .finish_non_exhaustive()
-    }
-}
-
-fn write_vcd_scope<W: io::Write, R>(
-    writer: &mut W,
-    scope_type: &str,
-    scope_name: &str,
-    f: impl FnOnce(&mut W) -> io::Result<R>,
-) -> io::Result<R> {
-    writeln!(writer, "$scope {scope_type} {scope_name} $end")?;
-    let retval = f(writer)?;
-    writeln!(writer, "$upscope $end")?;
-    Ok(retval)
-}
-
-macro_rules! trait_arg {
-    (
-        trait $Arg:ident {
-            $(
-                fn $fn:ident(&mut self) -> $ty:ty;
-            )*
-        }
-    ) => {
-        trait $Arg: Sized {
-            $(fn $fn(&mut self) -> $ty {
-                unreachable!()
-            })*
-        }
-
-        $(
-            impl $Arg for $ty {
-                fn $fn(&mut self) -> $ty {
-                    self.reborrow()
-                }
-            }
-        )*
-    };
-}
-
-trait_arg! {
-    trait Arg {
-        fn module(&mut self) -> ArgModule<'_>;
-        fn module_body(&mut self) -> ArgModuleBody<'_>;
-        fn in_type(&mut self) -> ArgInType<'_>;
-    }
-}
-
-struct ArgModule<'a> {
-    properties: &'a mut VcdWriterProperties,
-}
-
-impl<'a> ArgModule<'a> {
-    fn reborrow(&mut self) -> ArgModule<'_> {
-        ArgModule {
-            properties: self.properties,
-        }
-    }
-}
-
-struct ArgModuleBody<'a> {
-    properties: &'a mut VcdWriterProperties,
-}
-
-impl<'a> ArgModuleBody<'a> {
-    fn reborrow(&mut self) -> ArgModuleBody<'_> {
-        ArgModuleBody {
-            properties: self.properties,
-        }
-    }
-}
-
-struct ArgInType<'a> {
-    source_var_type: &'static str,
-    sink_var_type: &'static str,
-    duplex_var_type: &'static str,
-    properties: &'a mut VcdWriterProperties,
-}
-
-impl<'a> ArgInType<'a> {
-    fn reborrow(&mut self) -> ArgInType<'_> {
-        ArgInType {
-            source_var_type: self.source_var_type,
-            sink_var_type: self.sink_var_type,
-            duplex_var_type: self.duplex_var_type,
-            properties: self.properties,
-        }
-    }
-}
-
-trait WriteTrace: Copy {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()>;
-}
-
-impl WriteTrace for TraceDecl {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        match self {
-            Self::Scope(v) => v.write_trace(writer, arg),
-            Self::Scalar(v) => v.write_trace(writer, arg),
-        }
-    }
-}
-
-impl WriteTrace for TraceScalar {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        match self {
-            Self::UInt(v) => v.write_trace(writer, arg),
-            Self::SInt(v) => v.write_trace(writer, arg),
-            Self::Bool(v) => v.write_trace(writer, arg),
-            Self::FieldlessEnum(v) => v.write_trace(writer, arg),
-            Self::EnumDiscriminant(v) => v.write_trace(writer, arg),
-            Self::Clock(v) => v.write_trace(writer, arg),
-            Self::SyncReset(v) => v.write_trace(writer, arg),
-            Self::AsyncReset(v) => v.write_trace(writer, arg),
-        }
-    }
-}
-
-fn write_vcd_id<W: io::Write>(writer: &mut W, mut id: usize) -> io::Result<()> {
-    let min_char = b'!';
-    let max_char = b'~';
-    let base = (max_char - min_char + 1) as usize;
-    loop {
-        let digit = (id % base) as u8 + min_char;
-        id /= base;
-        writer.write_all(&[digit])?;
-        if id == 0 {
-            break;
-        }
-    }
-    Ok(())
-}
-
-fn write_escaped<W: io::Write>(writer: &mut W, value: impl fmt::Display) -> io::Result<()> {
-    // escaping rules from function GTKWave uses to decode VCD strings:
-    // https://github.com/gtkwave/gtkwave/blob/491f24d7e8619cfc1fcc65704ee5c967d1083c18/lib/libfst/fstapi.c#L7090
-    struct Wrapper<W>(W);
-    impl<W: io::Write> io::Write for Wrapper<W> {
-        fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
-            if buf.is_empty() {
-                return self.0.write(buf);
-            }
-            let mut retval = 0;
-            for &byte in buf {
-                match byte {
-                    b'\\' | b'\'' | b'"' | b'?' => self.0.write_all(&[b'\\', byte])?,
-                    b'\n' => self.0.write_all(br"\n")?,
-                    b'\r' => self.0.write_all(br"\r")?,
-                    b'\t' => self.0.write_all(br"\t")?,
-                    0x7 => self.0.write_all(br"\a")?,
-                    0x8 => self.0.write_all(br"\b")?,
-                    0xC => self.0.write_all(br"\f")?,
-                    0xB => self.0.write_all(br"\v")?,
-                    _ => {
-                        if byte.is_ascii_graphic() {
-                            self.0.write_all(&[byte])?;
-                        } else {
-                            write!(self.0, r"\x{byte:02x}")?;
-                        }
-                    }
-                }
-                retval += 1;
-            }
-            Ok(retval)
-        }
-
-        fn flush(&mut self) -> io::Result<()> {
-            self.0.flush()
-        }
-    }
-    write!(Wrapper(writer), "{value}")
-}
-
-fn is_unescaped_verilog_identifier(ident: &str) -> bool {
-    // we only allow ascii, so we can just check bytes
-    let Some((&first, rest)) = ident.as_bytes().split_first() else {
-        return false; // empty string is not an identifier
-    };
-    (first.is_ascii_alphabetic() || first == b'_')
-        && rest
-            .iter()
-            .all(|&ch| ch.is_ascii_alphanumeric() || ch == b'_' || ch == b'$')
-}
-
-fn write_vcd_var<W: io::Write>(
-    properties: &mut VcdWriterProperties,
-    memory_element_part_body: MemoryElementPartBody,
-    writer: &mut W,
-    var_type: &str,
-    size: usize,
-    location: TraceLocation,
-    name: &str,
-) -> io::Result<()> {
-    let id = match location {
-        TraceLocation::Scalar(id) => id.as_usize(),
-        TraceLocation::Memory(TraceMemoryLocation {
-            id,
-            depth,
-            stride: _,
-            start,
-            len,
-        }) => {
-            let MemoryProperties {
-                element_parts,
-                element_part_index,
-                element_index,
-            } = &mut properties.memory_properties[id.as_usize()];
-            let first_id;
-            if let Some(element_part) = element_parts.get(*element_part_index) {
-                first_id = element_part.first_id;
-            } else {
-                first_id = properties.next_scalar_id;
-                properties.next_scalar_id += depth;
-                element_parts.push(MemoryElementPart {
-                    first_id,
-                    start,
-                    len,
-                    body: memory_element_part_body,
-                });
-            }
-            *element_part_index += 1;
-            first_id + *element_index
-        }
-    };
-    write!(writer, "$var {var_type} {size} ")?;
-    write_vcd_id(writer, id)?;
-    writer.write_all(b" ")?;
-    if !is_unescaped_verilog_identifier(name) {
-        writer.write_all(b"\\")?;
-    }
-    write_escaped(writer, name)?;
-    writer.write_all(b" $end\n")
-}
-
-impl WriteTrace for TraceUInt {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgInType {
-            source_var_type,
-            sink_var_type,
-            duplex_var_type,
-            properties,
-        } = arg.in_type();
-        let Self {
-            location,
-            name,
-            ty,
-            flow,
-        } = self;
-        let mut var_type = match flow {
-            Flow::Source => source_var_type,
-            Flow::Sink => sink_var_type,
-            Flow::Duplex => duplex_var_type,
-        };
-        if ty.width() == 0 {
-            var_type = "string";
-        }
-        write_vcd_var(
-            properties,
-            MemoryElementPartBody::Scalar,
-            writer,
-            var_type,
-            ty.width(),
-            location,
-            &name,
-        )
-    }
-}
-
-impl WriteTrace for TraceSInt {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            ty,
-            flow,
-        } = self;
-        TraceUInt {
-            location,
-            name,
-            ty: UInt::new_dyn(ty.width()),
-            flow,
-        }
-        .write_trace(writer, arg)
-    }
-}
-
-impl WriteTrace for TraceBool {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            flow,
-        } = self;
-        TraceUInt {
-            location,
-            name,
-            flow,
-            ty: UInt::new_dyn(1),
-        }
-        .write_trace(writer, arg)
-    }
-}
-
-impl WriteTrace for TraceFieldlessEnum {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            ty,
-            flow,
-        } = self;
-        TraceEnumDiscriminant {
-            location,
-            name,
-            ty,
-            flow,
-        }
-        .write_trace(writer, arg)
-    }
-}
-
-impl WriteTrace for TraceEnumDiscriminant {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgInType {
-            source_var_type: _,
-            sink_var_type: _,
-            duplex_var_type: _,
-            properties,
-        } = arg.in_type();
-        let Self {
-            location,
-            name,
-            ty,
-            flow: _,
-        } = self;
-        write_vcd_var(
-            properties,
-            MemoryElementPartBody::EnumDiscriminant { ty },
-            writer,
-            "string",
-            1,
-            location,
-            &name,
-        )
-    }
-}
-
-impl WriteTrace for TraceClock {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            flow,
-        } = self;
-        TraceBool {
-            location,
-            name,
-            flow,
-        }
-        .write_trace(writer, arg)
-    }
-}
-
-impl WriteTrace for TraceSyncReset {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            flow,
-        } = self;
-        TraceBool {
-            location,
-            name,
-            flow,
-        }
-        .write_trace(writer, arg)
-    }
-}
-
-impl WriteTrace for TraceAsyncReset {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            flow,
-        } = self;
-        TraceBool {
-            location,
-            name,
-            flow,
-        }
-        .write_trace(writer, arg)
-    }
-}
-
-impl WriteTrace for TraceScope {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        match self {
-            Self::Module(v) => v.write_trace(writer, arg),
-            Self::Instance(v) => v.write_trace(writer, arg),
-            Self::Mem(v) => v.write_trace(writer, arg),
-            Self::MemPort(v) => v.write_trace(writer, arg),
-            Self::Wire(v) => v.write_trace(writer, arg),
-            Self::Reg(v) => v.write_trace(writer, arg),
-            Self::ModuleIO(v) => v.write_trace(writer, arg),
-            Self::Bundle(v) => v.write_trace(writer, arg),
-            Self::Array(v) => v.write_trace(writer, arg),
-            Self::EnumWithFields(v) => v.write_trace(writer, arg),
-        }
-    }
-}
-
-impl WriteTrace for TraceModule {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModule { properties } = arg.module();
-        let Self { name, children } = self;
-        write_vcd_scope(writer, "module", &name, |writer| {
-            for child in children {
-                child.write_trace(writer, ArgModuleBody { properties })?;
-            }
-            Ok(())
-        })
-    }
-}
-
-impl WriteTrace for TraceInstance {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
-        let Self {
-            name: _,
-            instance_io,
-            module,
-            ty: _,
-        } = self;
-        instance_io.write_trace(
-            writer,
-            ArgInType {
-                source_var_type: "wire",
-                sink_var_type: "wire",
-                duplex_var_type: "wire",
-                properties,
-            },
-        )?;
-        module.write_trace(writer, ArgModule { properties })
-    }
-}
-
-impl WriteTrace for TraceMem {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
-        let Self {
-            id,
-            name,
-            stride: _,
-            element_type,
-            ports,
-            array_type,
-        } = self;
-        write_vcd_scope(writer, "struct", &*name, |writer| {
-            write_vcd_scope(writer, "struct", "contents", |writer| {
-                for element_index in 0..array_type.len() {
-                    write_vcd_scope(writer, "struct", &format!("[{element_index}]"), |writer| {
-                        properties.memory_properties[id.as_usize()].element_index = element_index;
-                        properties.memory_properties[id.as_usize()].element_part_index = 0;
-                        element_type.write_trace(
-                            writer,
-                            ArgInType {
-                                source_var_type: "reg",
-                                sink_var_type: "reg",
-                                duplex_var_type: "reg",
-                                properties,
-                            },
-                        )
-                    })?;
-                }
-                Ok(())
-            })?;
-            for port in ports {
-                port.write_trace(writer, ArgModuleBody { properties })?;
-            }
-            Ok(())
-        })
-    }
-}
-
-impl WriteTrace for TraceMemPort {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
-        let Self {
-            name: _,
-            bundle,
-            ty: _,
-        } = self;
-        bundle.write_trace(
-            writer,
-            ArgInType {
-                source_var_type: "wire",
-                sink_var_type: "wire",
-                duplex_var_type: "wire",
-                properties,
-            },
-        )
-    }
-}
-
-impl WriteTrace for TraceWire {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
-        let Self {
-            name: _,
-            child,
-            ty: _,
-        } = self;
-        child.write_trace(
-            writer,
-            ArgInType {
-                source_var_type: "wire",
-                sink_var_type: "wire",
-                duplex_var_type: "wire",
-                properties,
-            },
-        )
-    }
-}
-
-impl WriteTrace for TraceReg {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
-        let Self {
-            name: _,
-            child,
-            ty: _,
-        } = self;
-        child.write_trace(
-            writer,
-            ArgInType {
-                source_var_type: "reg",
-                sink_var_type: "reg",
-                duplex_var_type: "reg",
-                properties,
-            },
-        )
-    }
-}
-
-impl WriteTrace for TraceModuleIO {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
-        let Self {
-            name: _,
-            child,
-            ty: _,
-            flow: _,
-        } = self;
-        child.write_trace(
-            writer,
-            ArgInType {
-                source_var_type: "wire",
-                sink_var_type: "wire",
-                duplex_var_type: "wire",
-                properties,
-            },
-        )
-    }
-}
-
-impl WriteTrace for TraceBundle {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let mut arg = arg.in_type();
-        let Self {
-            name,
-            fields,
-            ty: _,
-            flow: _,
-        } = self;
-        write_vcd_scope(writer, "struct", &name, |writer| {
-            for field in fields {
-                field.write_trace(writer, arg.reborrow())?;
-            }
-            Ok(())
-        })
-    }
-}
-
-impl WriteTrace for TraceArray {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let mut arg = arg.in_type();
-        let Self {
-            name,
-            elements,
-            ty: _,
-            flow: _,
-        } = self;
-        write_vcd_scope(writer, "struct", &name, |writer| {
-            for element in elements {
-                element.write_trace(writer, arg.reborrow())?;
-            }
-            Ok(())
-        })
-    }
-}
-
-impl WriteTrace for TraceEnumWithFields {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let mut arg = arg.in_type();
-        let Self {
-            name,
-            discriminant,
-            non_empty_fields,
-            ty: _,
-            flow: _,
-        } = self;
-        write_vcd_scope(writer, "struct", &name, |writer| {
-            discriminant.write_trace(writer, arg.reborrow())?;
-            for field in non_empty_fields {
-                field.write_trace(writer, arg.reborrow())?;
-            }
-            Ok(())
-        })
-    }
-}
-
-impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
-    type Error = io::Error;
-    type TraceWriter = VcdWriter<W>;
-
-    fn write_decls(
-        self,
-        module: TraceModule,
-        trace_scalar_id_count: usize,
-        trace_memory_id_count: usize,
-    ) -> Result<Self::TraceWriter, Self::Error> {
-        let Self {
-            mut writer,
-            timescale,
-        } = self;
-        writeln!(writer, "$timescale {} $end", vcd_timescale(timescale))?;
-        let mut properties = VcdWriterProperties {
-            next_scalar_id: trace_scalar_id_count,
-            memory_properties: (0..trace_memory_id_count)
-                .map(|_| MemoryProperties {
-                    element_parts: Vec::with_capacity(8),
-                    element_part_index: 0,
-                    element_index: 0,
-                })
-                .collect(),
-        };
-        module.write_trace(
-            &mut writer,
-            ArgModule {
-                properties: &mut properties,
-            },
-        )?;
-        writeln!(writer, "$enddefinitions $end")?;
-        writeln!(writer, "$dumpvars")?;
-        Ok(VcdWriter {
-            writer,
-            finished_init: false,
-            timescale,
-            properties,
-        })
-    }
-}
-
-enum MemoryElementPartBody {
-    Scalar,
-    EnumDiscriminant { ty: Enum },
-}
-
-struct MemoryElementPart {
-    first_id: usize,
-    start: usize,
-    len: usize,
-    body: MemoryElementPartBody,
-}
-
-struct MemoryProperties {
-    element_parts: Vec<MemoryElementPart>,
-    element_part_index: usize,
-    element_index: usize,
-}
-
-struct VcdWriterProperties {
-    next_scalar_id: usize,
-    memory_properties: Box<[MemoryProperties]>,
-}
-
-pub struct VcdWriter<W: io::Write + 'static> {
-    writer: W,
-    finished_init: bool,
-    timescale: SimDuration,
-    properties: VcdWriterProperties,
-}
-
-impl<W: io::Write + 'static> VcdWriter<W> {
-    pub fn timescale(&self) -> SimDuration {
-        self.timescale
-    }
-}
-
-fn write_string_value_change(
-    writer: &mut impl io::Write,
-    value: impl fmt::Display,
-    id: usize,
-) -> io::Result<()> {
-    writer.write_all(b"s")?;
-    write_escaped(writer, value)?;
-    writer.write_all(b" ")?;
-    write_vcd_id(writer, id)?;
-    writer.write_all(b"\n")
-}
-
-fn write_bits_value_change(
-    writer: &mut impl io::Write,
-    value: &BitSlice,
-    id: usize,
-) -> io::Result<()> {
-    match value.len() {
-        0 => writer.write_all(b"s0 ")?,
-        1 => writer.write_all(if value[0] { b"1" } else { b"0" })?,
-        _ => {
-            writer.write_all(b"b")?;
-            let mut any_ones = false;
-            for bit in value.iter().rev() {
-                if *bit {
-                    any_ones = true;
-                    writer.write_all(b"1")?;
-                } else if any_ones {
-                    writer.write_all(b"0")?;
-                }
-            }
-            if !any_ones {
-                writer.write_all(b"0")?;
-            }
-            writer.write_all(b" ")?;
-        }
-    }
-    write_vcd_id(writer, id)?;
-    writer.write_all(b"\n")
-}
-
-fn write_enum_discriminant_value_change(
-    writer: &mut impl io::Write,
-    variant_index: usize,
-    ty: Enum,
-    id: usize,
-) -> io::Result<()> {
-    write_string_value_change(
-        writer,
-        format_args!(
-            "{} ({variant_index})",
-            ty.variants()
-                .get(variant_index)
-                .map(|v| &*v.name)
-                .unwrap_or("<invalid>"),
-        ),
-        id,
-    )
-}
-
-impl<W: io::Write> TraceWriter for VcdWriter<W> {
-    type Error = io::Error;
-
-    fn set_memory_element(
-        &mut self,
-        memory: TraceMemoryId,
-        element_index: usize,
-        element_data: &BitSlice,
-    ) -> Result<(), Self::Error> {
-        for &MemoryElementPart {
-            first_id,
-            start,
-            len,
-            ref body,
-        } in &self.properties.memory_properties[memory.as_usize()].element_parts
-        {
-            match body {
-                MemoryElementPartBody::Scalar => write_bits_value_change(
-                    &mut self.writer,
-                    &element_data[start..start + len],
-                    first_id + element_index,
-                )?,
-                MemoryElementPartBody::EnumDiscriminant { ty } => {
-                    let mut variant_index = 0;
-                    BitSlice::<usize, Lsb0>::from_element_mut(&mut variant_index)[..len]
-                        .clone_from_bitslice(&element_data[start..start + len]);
-                    write_enum_discriminant_value_change(
-                        &mut self.writer,
-                        variant_index,
-                        *ty,
-                        first_id + element_index,
-                    )?
-                }
-            }
-        }
-        Ok(())
-    }
-
-    fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
-        write_bits_value_change(&mut self.writer, value, id.as_usize())
-    }
-
-    fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
-        write_bits_value_change(&mut self.writer, value, id.as_usize())
-    }
-
-    fn finish_init(&mut self) -> Result<(), Self::Error> {
-        if mem::replace(&mut self.finished_init, true) {
-            return Ok(());
-        }
-        writeln!(self.writer, "$end")
-    }
-
-    fn change_time_to(&mut self, instant: SimInstant) -> Result<(), Self::Error> {
-        assert!(self.finished_init);
-        let mut instant_attos = (instant - SimInstant::START).as_attos();
-        instant_attos += self.timescale.as_attos() / 2;
-        let timestamp = instant_attos / self.timescale.as_attos();
-        writeln!(self.writer, "#{timestamp}")
-    }
-
-    fn flush(&mut self) -> Result<(), Self::Error> {
-        self.writer.flush()
-    }
-
-    fn close(mut self) -> Result<(), Self::Error> {
-        self.writer.flush()
-    }
-
-    fn set_signal_enum_discriminant(
-        &mut self,
-        id: TraceScalarId,
-        variant_index: usize,
-        ty: Enum,
-    ) -> Result<(), Self::Error> {
-        write_enum_discriminant_value_change(&mut self.writer, variant_index, ty, id.as_usize())
-    }
-}
-
-impl<W: io::Write> fmt::Debug for VcdWriter<W> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let Self {
-            writer: _,
-            finished_init,
-            timescale,
-            properties: _,
-        } = self;
-        f.debug_struct("VcdWriter")
-            .field("finished_init", finished_init)
-            .field("timescale", timescale)
-            .finish_non_exhaustive()
-    }
-}

crates/fayalite/src/util.rs

@@ -24,8 +24,7 @@ pub use scoped_ref::ScopedRef;
 
 #[doc(inline)]
 pub use misc::{
-    get_many_mut, interned_bit, iter_eq_by, BitSliceWriteWithBase, DebugAsDisplay,
+    interned_bit, iter_eq_by, BitSliceWriteWithBase, DebugAsDisplay, DebugAsRawString, MakeMutSlice,
-    DebugAsRawString, MakeMutSlice, RcWriter,
 };
 
 pub mod job_server;

crates/fayalite/src/util/misc.rs

@@ -3,7 +3,6 @@
 use crate::intern::{Intern, Interned};
 use bitvec::{bits, order::Lsb0, slice::BitSlice, view::BitView};
 use std::{
-    cell::Cell,
     fmt::{self, Debug, Write},
     rc::Rc,
     sync::{Arc, OnceLock},
@@ -95,15 +94,9 @@ pub fn interned_bit(v: bool) -> Interned<BitSlice> {
     RETVAL.get_or_init(|| [bits![0; 1].intern(), bits![1; 1].intern()])[v as usize]
 }
 
-#[derive(Copy, Clone)]
+#[derive(Copy, Clone, Debug)]
 pub struct BitSliceWriteWithBase<'a>(pub &'a BitSlice);
 
-impl<'a> Debug for BitSliceWriteWithBase<'a> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        write!(f, "{self:#x}")
-    }
-}
-
 impl BitSliceWriteWithBase<'_> {
     fn fmt_with_base<const BITS_PER_DIGIT: usize, const UPPER_CASE: bool>(
         self,
@@ -162,66 +155,3 @@ impl fmt::UpperHex for BitSliceWriteWithBase<'_> {
         self.fmt_with_base::<4, true>(f)
     }
 }
-
-#[inline]
-#[track_caller]
-pub fn get_many_mut<T, const N: usize>(slice: &mut [T], indexes: [usize; N]) -> [&mut T; N] {
-    for i in 0..N {
-        for j in 0..i {
-            assert!(indexes[i] != indexes[j], "duplicate index");
-        }
-        assert!(indexes[i] < slice.len(), "index out of bounds");
-    }
-    // Safety: checked that no indexes are duplicates and no indexes are out of bounds
-    unsafe {
-        let base = slice.as_mut_ptr(); // convert to a raw pointer before loop to avoid aliasing with &mut [T]
-        std::array::from_fn(|i| &mut *base.add(indexes[i]))
-    }
-}
-
-#[derive(Clone, Default)]
-pub struct RcWriter(Rc<Cell<Vec<u8>>>);
-
-impl Debug for RcWriter {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.borrow_impl(|buf| {
-            f.debug_tuple("RcWriter")
-                .field(&DebugAsDisplay(format_args!("b\"{}\"", buf.escape_ascii())))
-                .finish()
-        })
-    }
-}
-
-impl RcWriter {
-    fn borrow_impl<R>(&self, f: impl FnOnce(&mut Vec<u8>) -> R) -> R {
-        let buf = Cell::take(&self.0);
-        struct PutBackOnDrop<'a> {
-            buf: Vec<u8>,
-            this: &'a RcWriter,
-        }
-        impl Drop for PutBackOnDrop<'_> {
-            fn drop(&mut self) {
-                self.this.0.set(std::mem::take(&mut self.buf));
-            }
-        }
-        let mut buf = PutBackOnDrop { buf, this: self };
-        f(&mut buf.buf)
-    }
-    pub fn borrow<R>(&mut self, f: impl FnOnce(&mut Vec<u8>) -> R) -> R {
-        self.borrow_impl(f)
-    }
-    pub fn take(&mut self) -> Vec<u8> {
-        Cell::take(&self.0)
-    }
-}
-
-impl std::io::Write for RcWriter {
-    fn write(&mut self, buf: &[u8]) -> std::io::Result<usize> {
-        self.borrow(|v| v.extend_from_slice(buf));
-        Ok(buf.len())
-    }
-
-    fn flush(&mut self) -> std::io::Result<()> {
-        Ok(())
-    }
-}

crates/fayalite/src/util/ready_valid.rs

@@ -49,18 +49,6 @@ impl<T: Type> ReadyValid<T> {
     }
 }
 
-/// This debug port is only meant to assist the formal proof of the queue.
-#[cfg(test)]
-#[doc(hidden)]
-#[hdl]
-pub struct QueueDebugPort<Element, Index> {
-    #[hdl(flip)]
-    index_to_check: Index,
-    stored: Element,
-    inp_index: Index,
-    out_index: Index,
-}
-
 #[hdl_module]
 pub fn queue<T: Type>(
     ty: T,
@@ -190,22 +178,6 @@ pub fn queue<T: Type>(
             }
         }
     }
-    // These debug ports expose some internal state during the Induction phase
-    // of Formal Verification. They are not present in normal use.
-    #[cfg(test)]
-    {
-        #[hdl]
-        let dbg: QueueDebugPort<T, UInt> = m.output(QueueDebugPort[ty][index_ty]);
-        // read the memory word currently stored at some fixed index
-        let debug_port = mem.new_read_port();
-        connect(debug_port.addr, dbg.index_to_check);
-        connect(debug_port.en, true);
-        connect(debug_port.clk, cd.clk);
-        connect(dbg.stored, debug_port.data);
-        // also expose the current read and write indices
-        connect(dbg.inp_index, inp_index_reg);
-        connect(dbg.out_index, out_index_reg);
-    }
 }
 
 #[cfg(test)]
@@ -224,23 +196,13 @@ mod tests {
             format_args!("test_queue_{capacity}_{inp_ready_is_comb}_{out_valid_is_comb}"),
             queue_test(capacity, inp_ready_is_comb, out_valid_is_comb),
             FormalMode::Prove,
-            2,
+            14,
             None,
             ExportOptions {
                 simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
                 ..ExportOptions::default()
             },
         );
-        /// Formal verification of the FIFO queue
-        ///
-        /// The strategy derives from the observation that, if we filter its
-        /// input and output streams to consider just one in every N reads and
-        /// writes (where N is the FIFO capacity), then the FIFO effectively
-        /// behaves as a one-entry FIFO.
-        ///
-        /// In particular, any counterexample of the full FIFO behaving badly
-        /// will also be caught by one of the filtered versions (one which
-        /// happens to be in phase with the offending input or output).
         #[hdl_module]
         fn queue_test(capacity: NonZeroUsize, inp_ready_is_comb: bool, out_valid_is_comb: bool) {
             #[hdl]
@@ -255,8 +217,6 @@ mod tests {
                     rst: formal_reset().to_reset(),
                 },
             );
-
-            // random input data
             #[hdl]
             let inp_data: HdlOption<UInt<8>> = wire();
             #[hdl]
@@ -265,26 +225,16 @@ mod tests {
             } else {
                 connect(inp_data, HdlNone());
             }
-
-            // assert output ready at random
             #[hdl]
             let out_ready: Bool = wire();
             connect(out_ready, any_seq(Bool));
-
+            let index_ty: UInt<32> = UInt::TYPE;
-            // The current number of elements in the FIFO ranges from zero to
-            // maximum capacity, inclusive.
-            let count_ty = UInt::range_inclusive(0..=capacity.get());
-            // type for counters that wrap around at the FIFO capacity
-            let index_ty = UInt::range(0..capacity.get());
-
-            // among all entries of the FIFO internal circular memory, choose
-            // one at random to check
             #[hdl]
-            let index_to_check = wire(index_ty);
+            let index_to_check = wire();
             connect(index_to_check, any_const(index_ty));
-            hdl_assume(clk, index_to_check.cmp_lt(capacity.get()), "");
+            let index_max = !index_ty.zero();
-
+            // we saturate at index_max, so only check indexes where we properly maintain position
-            // instantiate and connect the queue
+            hdl_assume(clk, index_to_check.cmp_ne(index_max), "");
             #[hdl]
             let dut = instance(queue(
                 UInt[ConstUsize::<8>],
@@ -295,172 +245,109 @@ mod tests {
             connect(dut.cd, cd);
             connect(dut.inp.data, inp_data);
             connect(dut.out.ready, out_ready);
+            hdl_assume(
+                clk,
+                index_to_check.cmp_ne(!Expr::ty(index_to_check).zero()),
+                "",
+            );
 
-            // Keep an independent count of words in the FIFO. Ensure that
-            // it's always correct, and never overflows.
             #[hdl]
-            let expected_count_reg = reg_builder().clock_domain(cd).reset(count_ty.zero());
+            let expected_count_reg = reg_builder().clock_domain(cd).reset(0u32);
+            #[hdl]
+            let next_expected_count = wire();
+            connect(next_expected_count, expected_count_reg);
+            connect(expected_count_reg, next_expected_count);
             #[hdl]
             if ReadyValid::firing(dut.inp) & !ReadyValid::firing(dut.out) {
-                hdl_assert(clk, expected_count_reg.cmp_ne(capacity.get()), "");
+                connect_any(next_expected_count, expected_count_reg + 1u8);
-                connect_any(expected_count_reg, expected_count_reg + 1u8);
             } else if !ReadyValid::firing(dut.inp) & ReadyValid::firing(dut.out) {
-                hdl_assert(clk, expected_count_reg.cmp_ne(count_ty.zero()), "");
+                connect_any(next_expected_count, expected_count_reg - 1u8);
-                connect_any(expected_count_reg, expected_count_reg - 1u8);
             }
-            hdl_assert(clk, expected_count_reg.cmp_eq(dut.count), "");
+            hdl_assert(cd.clk, expected_count_reg.cmp_eq(dut.count), "");
+
+            #[hdl]
+            let prev_out_ready_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
+            connect_any(
+                prev_out_ready_reg,
+                (prev_out_ready_reg << 1) | out_ready.cast_to(UInt[1]),
+            );
+            #[hdl]
+            let prev_inp_valid_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
+            connect_any(
+                prev_inp_valid_reg,
+                (prev_inp_valid_reg << 1) | HdlOption::is_some(inp_data).cast_to(UInt[1]),
+            );
+            hdl_assume(
+                clk,
+                (prev_out_ready_reg & prev_inp_valid_reg).cmp_ne(0u8),
+                "",
+            );
 
-            // keep an independent write index into the FIFO's circular buffer
             #[hdl]
             let inp_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
             #[hdl]
-            if ReadyValid::firing(dut.inp) {
+            let stored_inp_data_reg = reg_builder().clock_domain(cd).reset(0u8);
+
+            #[hdl]
+            if let HdlSome(data) = ReadyValid::firing_data(dut.inp) {
                 #[hdl]
-                if inp_index_reg.cmp_ne(capacity.get() - 1) {
+                if inp_index_reg.cmp_lt(index_max) {
                     connect_any(inp_index_reg, inp_index_reg + 1u8);
-                } else {
+                    #[hdl]
-                    connect_any(inp_index_reg, 0_hdl_u0);
+                    if inp_index_reg.cmp_eq(index_to_check) {
+                        connect(stored_inp_data_reg, data);
+                    }
                 }
             }
 
-            // keep an independent read index into the FIFO's circular buffer
+            #[hdl]
+            if inp_index_reg.cmp_lt(index_to_check) {
+                hdl_assert(clk, stored_inp_data_reg.cmp_eq(0u8), "");
+            }
+
             #[hdl]
             let out_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
             #[hdl]
-            if ReadyValid::firing(dut.out) {
+            let stored_out_data_reg = reg_builder().clock_domain(cd).reset(0u8);
+
+            #[hdl]
+            if let HdlSome(data) = ReadyValid::firing_data(dut.out) {
                 #[hdl]
-                if out_index_reg.cmp_ne(capacity.get() - 1) {
+                if out_index_reg.cmp_lt(index_max) {
                     connect_any(out_index_reg, out_index_reg + 1u8);
-                } else {
-                    connect_any(out_index_reg, 0_hdl_u0);
-                }
-            }
-
-            // filter the input data stream, predicated by the read index
-            // matching the chosen position in the FIFO's circular buffer
-            #[hdl]
-            let inp_index_matches = wire();
-            connect(inp_index_matches, inp_index_reg.cmp_eq(index_to_check));
-            #[hdl]
-            let inp_firing_data = wire();
-            connect(inp_firing_data, HdlNone());
-            #[hdl]
-            if inp_index_matches {
-                connect(inp_firing_data, ReadyValid::firing_data(dut.inp));
-            }
-
-            // filter the output data stream, predicated by the write index
-            // matching the chosen position in the FIFO's circular buffer
-            #[hdl]
-            let out_index_matches = wire();
-            connect(out_index_matches, out_index_reg.cmp_eq(index_to_check));
-            #[hdl]
-            let out_firing_data = wire();
-            connect(out_firing_data, HdlNone());
-            #[hdl]
-            if out_index_matches {
-                connect(out_firing_data, ReadyValid::firing_data(dut.out));
-            }
-
-            // Implement a one-entry FIFO and ensure its equivalence to the
-            // filtered FIFO.
-            //
-            // the holding register for our one-entry FIFO
-            #[hdl]
-            let stored_reg = reg_builder().clock_domain(cd).reset(HdlNone());
-            #[hdl]
-            match stored_reg {
-                // If the holding register is empty...
-                HdlNone => {
                     #[hdl]
-                    match inp_firing_data {
+                    if out_index_reg.cmp_eq(index_to_check) {
-                        // ... and we are not receiving data, then we must not
+                        connect(stored_out_data_reg, data);
-                        // transmit any data.
-                        HdlNone => hdl_assert(clk, HdlOption::is_none(out_firing_data), ""),
-                        // If we are indeed receiving some data...
-                        HdlSome(data_in) => {
-                            #[hdl]
-                            match out_firing_data {
-                                // ... and transmitting at the same time, we
-                                // must be transmitting the input data itself,
-                                // since the holding register is empty.
-                                HdlSome(data_out) => hdl_assert(clk, data_out.cmp_eq(data_in), ""),
-                                // If we are receiving, but not transmitting,
-                                // store the received data in the holding
-                                // register.
-                                HdlNone => connect(stored_reg, HdlSome(data_in)),
-                            }
-                        }
-                    }
-                }
-                // If there is some value stored in the holding register...
-                HdlSome(stored) => {
-                    #[hdl]
-                    match out_firing_data {
-                        // ... and we are not transmitting it, we cannot
-                        // receive any more data.
-                        HdlNone => hdl_assert(clk, HdlOption::is_none(inp_firing_data), ""),
-                        // If we are transmitting a previously stored value...
-                        HdlSome(data_out) => {
-                            // ... it must be the same data we stored earlier.
-                            hdl_assert(clk, data_out.cmp_eq(stored), "");
-                            // Also, accept new data, if any. Otherwise,
-                            // let the holding register become empty.
-                            connect(stored_reg, inp_firing_data);
-                        }
                     }
                 }
             }
 
-            // from now on, some extra assertions in order to pass induction
-
-            // sync the holding register, when it's occupied, to the
-            // corresponding entry in the FIFO's circular buffer
-            connect(dut.dbg.index_to_check, index_to_check);
             #[hdl]
-            if let HdlSome(stored) = stored_reg {
+            if out_index_reg.cmp_lt(index_to_check) {
-                hdl_assert(clk, stored.cmp_eq(dut.dbg.stored), "");
+                hdl_assert(clk, stored_out_data_reg.cmp_eq(0u8), "");
             }
 
-            // sync the read and write indices
+            hdl_assert(clk, inp_index_reg.cmp_ge(out_index_reg), "");
-            hdl_assert(clk, inp_index_reg.cmp_eq(dut.dbg.inp_index), "");
-            hdl_assert(clk, out_index_reg.cmp_eq(dut.dbg.out_index), "");
 
-            // the indices should never go past the capacity, but induction
-            // doesn't know that...
-            hdl_assert(clk, inp_index_reg.cmp_lt(capacity.get()), "");
-            hdl_assert(clk, out_index_reg.cmp_lt(capacity.get()), "");
-
-            // strongly constrain the state of the holding register
-            //
-            // The holding register is full if and only if the corresponding
-            // FIFO entry was written to and not yet read. In other words, if
-            // the number of pending reads until the chosen entry is read out
-            // is greater than the current FIFO count, then the entry couldn't
-            // be in the FIFO in the first place.
             #[hdl]
-            let pending_reads: UInt = wire(index_ty);
+            if inp_index_reg.cmp_lt(index_max) & out_index_reg.cmp_lt(index_max) {
-            // take care of wrap-around when subtracting indices, add the
+                hdl_assert(
-            // capacity amount to keep the result positive if necessary
+                    clk,
-            #[hdl]
+                    expected_count_reg.cmp_eq(inp_index_reg - out_index_reg),
-            if index_to_check.cmp_ge(out_index_reg) {
+                    "",
-                connect(pending_reads, index_to_check - out_index_reg);
+                );
             } else {
-                connect(
+                hdl_assert(
-                    pending_reads,
+                    clk,
-                    index_to_check + capacity.get() - out_index_reg,
+                    expected_count_reg.cmp_ge(inp_index_reg - out_index_reg),
+                    "",
                 );
             }
-            // check whether the chosen entry is in the FIFO
+
             #[hdl]
-            let expected_stored: Bool = wire();
+            if inp_index_reg.cmp_gt(index_to_check) & out_index_reg.cmp_gt(index_to_check) {
-            connect(expected_stored, pending_reads.cmp_lt(dut.count));
+                hdl_assert(clk, stored_inp_data_reg.cmp_eq(stored_out_data_reg), "");
-            // sync with the state of the holding register
+            }
-            hdl_assert(
-                clk,
-                expected_stored.cmp_eq(HdlOption::is_some(stored_reg)),
-                "",
-            );
         }
     }
 
@@ -543,24 +430,4 @@ mod tests {
     fn test_4_true_true() {
         test_queue(NonZero::new(4).unwrap(), true, true);
     }
-
-    #[test]
-    fn test_many_false_false() {
-        test_queue(NonZero::new((2 << 16) - 5).unwrap(), false, false);
-    }
-
-    #[test]
-    fn test_many_false_true() {
-        test_queue(NonZero::new((2 << 16) - 5).unwrap(), false, true);
-    }
-
-    #[test]
-    fn test_many_true_false() {
-        test_queue(NonZero::new((2 << 16) - 5).unwrap(), true, false);
-    }
-
-    #[test]
-    fn test_many_true_true() {
-        test_queue(NonZero::new((2 << 16) - 5).unwrap(), true, true);
-    }
 }

crates/fayalite/src/wire.rs

@@ -37,18 +37,6 @@ impl<T: Type> Wire<T> {
             ty: ty.canonical(),
         }
     }
-    pub fn from_canonical(v: Wire<CanonicalType>) -> Self {
-        let Wire {
-            name,
-            source_location,
-            ty,
-        } = v;
-        Self {
-            name,
-            source_location,
-            ty: T::from_canonical(ty),
-        }
-    }
     pub fn ty(&self) -> T {
         self.ty
     }

crates/fayalite/tests/formal.rs

@@ -1,295 +0,0 @@
-// SPDX-License-Identifier: LGPL-3.0-or-later
-// See Notices.txt for copyright information
-//! Formal tests in Fayalite
-
-use fayalite::{
-    cli::FormalMode,
-    clock::{Clock, ClockDomain},
-    expr::{CastTo, HdlPartialEq},
-    firrtl::ExportOptions,
-    formal::{any_const, any_seq, formal_reset, hdl_assert, hdl_assume},
-    hdl, hdl_module,
-    int::{Bool, DynSize, Size, UInt, UIntType},
-    module::{connect, connect_any, instance, memory, reg_builder, wire},
-    reset::ToReset,
-    testing::assert_formal,
-    ty::StaticType,
-};
-
-/// Test hidden state
-///
-/// Hidden state can cause problems for induction, since the formal engine
-/// can assign invalid values to the state registers, making it traverse
-/// valid but unreachable states.
-///
-/// One solution is to go sufficiently in the past so the engine is forced
-/// to eventually take a reachable state. This may be hampered by
-/// existence of loops, then assumptions may be added to break them.
-///
-/// Another solution is to "open the black box" and add additional
-/// assertions involving the hidden state, so that the unreachable states
-/// become invalid as well.
-///
-/// Both approaches are taken here.
-///
-/// See [Claire Wolf's presentation] and [Zipcpu blog article].
-///
-/// [Claire Wolf's presentation]: https://web.archive.org/web/20200115081517fw_/http://www.clifford.at/papers/2017/smtbmc-sby/
-/// [Zipcpu blog article]: https://zipcpu.com/blog/2018/03/10/induction-exercise.html
-mod hidden_state {
-    use super::*;
-    /// Test hidden state by shift registers
-    ///
-    /// The code implement the ideas from an article in the [Zipcpu blog]. Two
-    /// shift registers are fed from the same input, so they should always have
-    /// the same value. However the only observable is a comparison of their
-    /// last bit, all the others are hidden. To complicate matters, an enable
-    /// signal causes a loop in state space.
-    ///
-    /// [Zipcpu blog]: https://zipcpu.com/blog/2018/03/10/induction-exercise.html
-    #[test]
-    fn shift_register() {
-        enum ConstraintMode {
-            WithExtraAssertions,
-            WithExtraAssumptions,
-        }
-        use ConstraintMode::*;
-        #[hdl_module]
-        fn test_module(constraint_mode: ConstraintMode) {
-            #[hdl]
-            let clk: Clock = m.input();
-            #[hdl]
-            let cd = wire();
-            connect(
-                cd,
-                #[hdl]
-                ClockDomain {
-                    clk,
-                    rst: formal_reset().to_reset(),
-                },
-            );
-            // input signal for the shift registers
-            #[hdl]
-            let i: Bool = wire();
-            connect(i, any_seq(Bool));
-            // shift enable signal
-            #[hdl]
-            let en: Bool = wire();
-            connect(en, any_seq(Bool));
-            // comparison output
-            #[hdl]
-            let o: Bool = wire();
-            // shift registers, with enable
-            #[hdl]
-            let r1 = reg_builder().clock_domain(cd).reset(0u8);
-            #[hdl]
-            let r2 = reg_builder().clock_domain(cd).reset(0u8);
-            #[hdl]
-            if en {
-                connect_any(r1, (r1 << 1) | i.cast_to(UInt[1]));
-                connect_any(r2, (r2 << 1) | i.cast_to(UInt[1]));
-            }
-            // compare last bits of both shift registers
-            connect(o, r1[7].cmp_eq(r2[7]));
-
-            // what we want to prove: last bits are always equal
-            hdl_assert(clk, o, "");
-
-            // additional terms below are only needed to assist with the induction proof
-            match constraint_mode {
-                WithExtraAssertions => {
-                    // "Open the box": add assertions about hidden state.
-                    // In this case, the hidden bits are also always equal.
-                    hdl_assert(clk, r1.cmp_eq(r2), "");
-                }
-                WithExtraAssumptions => {
-                    // Break the loop, do not allow "en" to remain low forever
-                    #[hdl]
-                    let past_en_reg = reg_builder().clock_domain(cd).reset(false);
-                    connect(past_en_reg, en);
-                    hdl_assume(clk, past_en_reg | en, "");
-                }
-            }
-        }
-        // we need a minimum of 16 steps so we can constrain all eight shift register bits,
-        // given that we are allowed to disable the shift once every two cycles.
-        assert_formal(
-            "shift_register_with_assumptions",
-            test_module(WithExtraAssumptions),
-            FormalMode::Prove,
-            16,
-            None,
-            ExportOptions::default(),
-        );
-        // here a couple of cycles is enough
-        assert_formal(
-            "shift_register_with_assertions",
-            test_module(WithExtraAssertions),
-            FormalMode::Prove,
-            2,
-            None,
-            ExportOptions::default(),
-        );
-    }
-}
-
-/// Formal verification of designs containing memories
-///
-/// There is a trick for memories, described in the [Zipcpu blog].
-/// First, select a fixed but arbitrary memory address, monitoring all reads
-/// and writes made to it. Then, assert that anything read from that location
-/// matches the last stored value.
-///
-/// A difficulty for induction is that the memory represents [hidden_state]. A
-/// solution is to include an additional read port to the memory and assert
-/// that the memory location effectively contains the last stored value.
-/// This additional debug port is present only to assist the proof and is
-/// unused (optimized out) in actual use.
-///
-/// [Zipcpu blog]: <https://zipcpu.com/zipcpu/2018/07/13/memories.html>
-mod memory {
-    use super::*;
-
-    /// Test a simple 8-bit SRAM model
-    #[test]
-    fn test_sram() {
-        #[hdl]
-        struct WritePort<AddrWidth: Size> {
-            addr: UIntType<AddrWidth>,
-            data: UInt<8>,
-            en: Bool,
-        }
-        #[hdl]
-        struct ReadPort<AddrWidth: Size> {
-            addr: UIntType<AddrWidth>,
-            #[hdl(flip)]
-            data: UInt<8>,
-        }
-        /// This debug port is only meant to assist the proof.
-        /// For normal use in a design, a wrapper could be provided,
-        /// omitting this port.
-        /// The implementation is forbidden to use any information
-        /// provided on this port in its internal workings.
-        #[hdl]
-        struct DebugPort<AddrWidth: Size> {
-            selected: UIntType<AddrWidth>,
-            stored: UInt<8>,
-            wrote: Bool,
-        }
-        /// simple 1R1W SRAM model (one asynchronous read port and one
-        /// independent write port) with `n`-bit address width
-        #[hdl_module]
-        fn example_sram(n: usize) {
-            #[hdl]
-            let wr: WritePort<DynSize> = m.input(WritePort[n]);
-            #[hdl]
-            let rd: ReadPort<DynSize> = m.input(ReadPort[n]);
-            #[hdl]
-            let cd: ClockDomain = m.input();
-
-            // declare and connect the backing memory
-            #[hdl]
-            let mut mem = memory();
-            mem.depth(1 << n);
-            let read_port = mem.new_read_port();
-            let write_port = mem.new_write_port();
-            connect(write_port.clk, cd.clk);
-            connect(write_port.addr, wr.addr);
-            connect(write_port.en, wr.en);
-            connect(write_port.data, wr.data);
-            connect(write_port.mask, true);
-            connect(read_port.clk, cd.clk);
-            connect(read_port.addr, rd.addr);
-            connect(read_port.en, true);
-            connect(rd.data, read_port.data);
-
-            // To assist with induction, ensure that the chosen memory location
-            // really contains, always, the last value written to it.
-            #[hdl]
-            let dbg: DebugPort<DynSize> = m.input(DebugPort[n]);
-            let debug_port = mem.new_read_port();
-            connect(debug_port.en, true);
-            connect(debug_port.clk, cd.clk);
-            connect(debug_port.addr, dbg.selected);
-            #[hdl]
-            if dbg.wrote {
-                hdl_assert(cd.clk, debug_port.data.cmp_eq(dbg.stored), "");
-                // Try commenting out the assert above, induction will fail.
-                // Opening the trace, it can be seen that the memory contents
-                // and the stored value don't match, which is an unreachable
-                // state. By asserting the above, it will become invalid
-                // as well, so induction will skip this kind of situation.
-            }
-        }
-
-        /// formal verification of the SRAM module, parametrized by the
-        /// address bit-width
-        #[hdl_module]
-        fn test_module(n: usize) {
-            #[hdl]
-            let clk: Clock = m.input();
-            let cd = #[hdl]
-            ClockDomain {
-                clk,
-                rst: formal_reset().to_reset(),
-            };
-
-            // instantiate the SRAM model, connecting its inputs to
-            // a random sequence
-            #[hdl]
-            let rd: ReadPort<DynSize> = wire(ReadPort[n]);
-            connect(rd.addr, any_seq(UInt[n]));
-            #[hdl]
-            let wr: WritePort<DynSize> = wire(WritePort[n]);
-            connect(wr.addr, any_seq(UInt[n]));
-            connect(wr.data, any_seq(UInt::<8>::TYPE));
-            connect(wr.en, any_seq(Bool));
-            #[hdl]
-            let dut = instance(example_sram(n));
-            connect(dut.cd, cd);
-            connect(dut.rd, rd);
-            connect(dut.wr, wr);
-
-            // select a fixed but arbitrary test address
-            #[hdl]
-            let selected = wire(UInt[n]);
-            connect(selected, any_const(UInt[n]));
-            // store the last value written to that address
-            #[hdl]
-            let stored: UInt<8> = reg_builder().clock_domain(cd).reset(0u8);
-            // since memories are not initialized, track whether we wrote to the
-            // memory at least once
-            #[hdl]
-            let wrote: Bool = reg_builder().clock_domain(cd).reset(false);
-            // on a write, capture the last written value
-            #[hdl]
-            if wr.en & wr.addr.cmp_eq(selected) {
-                connect(stored, wr.data);
-                connect(wrote, true);
-            }
-            // on a read, assert that the read value is the same which was stored
-            #[hdl]
-            if rd.addr.cmp_eq(selected) & wrote {
-                hdl_assert(clk, rd.data.cmp_eq(stored), "");
-            }
-
-            // to assist induction, pass our state to the underlying instance
-            let dbg = #[hdl]
-            DebugPort {
-                selected,
-                stored,
-                wrote,
-            };
-            connect(dut.dbg, dbg);
-        }
-
-        assert_formal(
-            "sram",
-            test_module(8),
-            FormalMode::Prove,
-            2,
-            None,
-            ExportOptions::default(),
-        );
-    }
-}

crates/fayalite/tests/hdl_types.rs

@@ -31,8 +31,6 @@ pub enum E<T> {
     A,
     B(UInt<3>),
     C(T),
-    D(TyAlias2),
-    E(TyAlias<Bool, ConstUsize<1>, { 1 + 2 }>),
 }
 
 #[hdl(outline_generated)]
@@ -40,12 +38,6 @@ pub struct S2<T = ()> {
     pub v: E<T>,
 }
 
-#[hdl(outline_generated)]
-pub type TyAlias<T, Sz: Size, const C: usize, D = ()> = Array<S<T, Sz, D>, C>;
-
-#[hdl(outline_generated)]
-pub type TyAlias2 = TyAlias<UInt<8>, ConstUsize<24>, 5>;
-
 // check that #[hdl] properly handles hygiene
 macro_rules! types_in_macros {
     ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident, $f:ident, $A:ident, $B:ident, $C:ident, $D:ident, $E:ident, $F:ident) => {

crates/fayalite/tests/module.rs

@@ -2,8 +2,7 @@
 // See Notices.txt for copyright information
 use fayalite::{
     assert_export_firrtl, firrtl::ExportOptions, intern::Intern,
-    module::transform::simplify_enums::SimplifyEnumsKind, prelude::*, reset::ResetType,
+    module::transform::simplify_enums::SimplifyEnumsKind, prelude::*, ty::StaticType,
-    ty::StaticType,
 };
 use serde_json::json;
 
@@ -4027,321 +4026,3 @@ circuit check_enum_connect_any:
 ",
     };
 }
-
-#[hdl_module(outline_generated)]
-pub fn check_deduce_resets<T: ResetType>(ty: T) {
-    #[hdl]
-    let cd: ClockDomain<T> = m.input(ClockDomain[ty]);
-    #[hdl]
-    let my_reg = reg_builder().reset(0u8).clock_domain(cd);
-    #[hdl]
-    let u8_in: UInt<8> = m.input();
-    connect(my_reg, u8_in);
-    #[hdl]
-    let u8_out: UInt<8> = m.output();
-    connect(u8_out, my_reg);
-    #[hdl]
-    let enum_in: OneOfThree<Reset, AsyncReset, SyncReset> = m.input();
-    #[hdl]
-    let enum_out: OneOfThree<Reset, AsyncReset, SyncReset> = m.output();
-    #[hdl]
-    let reset_out: Reset = m.output();
-    connect(reset_out, cd.rst.to_reset());
-    #[hdl]
-    match enum_in {
-        OneOfThree::<_, _, _>::A(v) => {
-            connect(
-                enum_out,
-                OneOfThree[Reset][AsyncReset][SyncReset].A(cd.rst.to_reset()),
-            );
-            connect(reset_out, v);
-        }
-        OneOfThree::<_, _, _>::B(v) => {
-            connect(enum_out, OneOfThree[Reset][AsyncReset][SyncReset].B(v))
-        }
-        OneOfThree::<_, _, _>::C(v) => {
-            connect(enum_out, OneOfThree[Reset][AsyncReset][SyncReset].C(v))
-        }
-    }
-}
-
-#[test]
-fn test_deduce_resets() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let m = check_deduce_resets(Reset);
-    dbg!(m);
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_enums: None,
-            ..ExportOptions::default()
-        },
-        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
-circuit check_deduce_resets:
-    type Ty0 = {clk: Clock, rst: Reset}
-    type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
-    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
-        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
-        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
-        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
-        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
-        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
-        output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
-        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
-        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
-        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
-        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
-        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
-            A(_match_arm_value):
-                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
-                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
-            B(_match_arm_value_1):
-                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
-            C(_match_arm_value_2):
-                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
-",
-    };
-    fayalite::module::transform::deduce_resets::deduce_resets(m.canonical().intern_sized(), false)
-        .unwrap_err();
-    let m = fayalite::module::transform::deduce_resets::deduce_resets(
-        m.canonical().intern_sized(),
-        true,
-    )
-    .unwrap();
-    dbg!(m);
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_enums: None,
-            ..ExportOptions::default()
-        },
-        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
-circuit check_deduce_resets:
-    type Ty0 = {clk: Clock, rst: UInt<1>}
-    type Ty1 = {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}
-    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
-        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
-        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
-        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
-        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
-        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
-        output reset_out: UInt<1> @[module-XXXXXXXXXX.rs 10:1]
-        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
-        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
-        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
-        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
-        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
-            A(_match_arm_value):
-                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
-                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
-            B(_match_arm_value_1):
-                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
-            C(_match_arm_value_2):
-                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
-",
-    };
-    let m = check_deduce_resets(SyncReset);
-    dbg!(m);
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_enums: None,
-            ..ExportOptions::default()
-        },
-        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
-circuit check_deduce_resets:
-    type Ty0 = {clk: Clock, rst: UInt<1>}
-    type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
-    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
-        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
-        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
-        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
-        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
-        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
-        output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
-        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
-        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
-        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
-        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
-        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
-            A(_match_arm_value):
-                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
-                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
-            B(_match_arm_value_1):
-                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
-            C(_match_arm_value_2):
-                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
-",
-    };
-    let m = fayalite::module::transform::deduce_resets::deduce_resets(
-        m.canonical().intern_sized(),
-        false,
-    )
-    .unwrap();
-    dbg!(m);
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_enums: None,
-            ..ExportOptions::default()
-        },
-        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
-circuit check_deduce_resets:
-    type Ty0 = {clk: Clock, rst: UInt<1>}
-    type Ty1 = {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}
-    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
-        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
-        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
-        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
-        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
-        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
-        output reset_out: UInt<1> @[module-XXXXXXXXXX.rs 10:1]
-        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
-        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
-        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
-        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
-        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
-            A(_match_arm_value):
-                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
-                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
-            B(_match_arm_value_1):
-                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
-            C(_match_arm_value_2):
-                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
-",
-    };
-    let m = check_deduce_resets(AsyncReset);
-    dbg!(m);
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_enums: None,
-            ..ExportOptions::default()
-        },
-        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
-circuit check_deduce_resets:
-    type Ty0 = {clk: Clock, rst: AsyncReset}
-    type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
-    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
-        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
-        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
-        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
-        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
-        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
-        output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
-        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
-        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
-        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
-        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
-        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
-            A(_match_arm_value):
-                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
-                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
-            B(_match_arm_value_1):
-                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
-            C(_match_arm_value_2):
-                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
-",
-    };
-    let m = fayalite::module::transform::deduce_resets::deduce_resets(
-        m.canonical().intern_sized(),
-        false,
-    )
-    .unwrap();
-    dbg!(m);
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_enums: None,
-            ..ExportOptions::default()
-        },
-        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
-circuit check_deduce_resets:
-    type Ty0 = {clk: Clock, rst: AsyncReset}
-    type Ty1 = {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}
-    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
-        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
-        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
-        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
-        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
-        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
-        output reset_out: AsyncReset @[module-XXXXXXXXXX.rs 10:1]
-        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
-        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
-        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
-        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
-        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
-            A(_match_arm_value):
-                connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
-                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
-            B(_match_arm_value_1):
-                connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
-            C(_match_arm_value_2):
-                connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
-",
-    };
-}
-
-// intentionally not outline_generated to ensure we get correct macro hygiene
-#[hdl_module]
-pub fn check_cfgs<#[cfg(cfg_false_for_tests)] A: Type, #[cfg(cfg_true_for_tests)] B: Type>(
-    #[cfg(cfg_false_for_tests)] a: A,
-    #[cfg(cfg_true_for_tests)] b: B,
-) {
-    #[hdl]
-    struct S<#[cfg(cfg_false_for_tests)] A, #[cfg(cfg_true_for_tests)] B> {
-        #[cfg(cfg_false_for_tests)]
-        a: A,
-        #[cfg(cfg_true_for_tests)]
-        b: B,
-    }
-    #[hdl]
-    #[cfg(cfg_false_for_tests)]
-    let i_a: A = m.input(a);
-    #[hdl]
-    #[cfg(cfg_true_for_tests)]
-    let i_b: B = m.input(b);
-    #[hdl]
-    let w: S<UInt<8>> = wire();
-    #[cfg(cfg_false_for_tests)]
-    {
-        #[hdl]
-        let o_a: A = m.output(a);
-        connect(o_a, w.a.cast_bits_to(a));
-        connect_any(w.a, i_a.cast_to_bits());
-    }
-    #[cfg(cfg_true_for_tests)]
-    {
-        #[hdl]
-        let o_b: B = m.output(b);
-        connect(o_b, w.b.cast_bits_to(b));
-        connect_any(w.b, i_b.cast_to_bits());
-    }
-}
-
-#[test]
-fn test_cfgs() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let m = check_cfgs(UInt[8]);
-    dbg!(m);
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        "/test/check_cfgs.fir": r"FIRRTL version 3.2.0
-circuit check_cfgs:
-    type Ty0 = {b: UInt<8>}
-    module check_cfgs: @[the_test_file.rs 9962:1]
-        input i_b: UInt<8> @[the_test_file.rs 9979:20]
-        output o_b: UInt<8> @[the_test_file.rs 9992:24]
-        wire w: Ty0 @[the_test_file.rs 9981:25]
-        connect o_b, w.b @[the_test_file.rs 9993:9]
-        connect w.b, i_b @[the_test_file.rs 9994:9]
-",
-    };
-}

crates/fayalite/tests/sim/expected/connect_const.txt

@@ -1,142 +0,0 @@
-Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                memories: StatePartLayout<Memories> {
-                    len: 0,
-                    debug_data: [],
-                    layout_data: [],
-                    ..
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:1:1
-                0: Const {
-                    dest: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
-                    value: 0x5,
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(0), // (0x5) SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                2: Return,
-            ],
-            ..
-        },
-        pc: 2,
-        memory_write_log: [],
-        memories: StatePart {
-            value: [],
-        },
-        small_slots: StatePart {
-            value: [],
-        },
-        big_slots: StatePart {
-            value: [
-                5,
-                5,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::connect_const,
-        instantiated: Module {
-            name: connect_const,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::connect_const,
-            instantiated: Module {
-                name: connect_const,
-                ..
-            },
-        }.o: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "connect_const",
-        children: [
-            TraceModuleIO {
-                name: "o",
-                child: TraceUInt {
-                    location: TraceScalarId(0),
-                    name: "o",
-                    ty: UInt<8>,
-                    flow: Sink,
-                },
-                ty: UInt<8>,
-                flow: Sink,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(0),
-                ty: UInt<8>,
-            },
-            state: 0x05,
-            last_state: 0x05,
-        },
-    ],
-    trace_memories: {},
-    trace_writers: [],
-    instant: 0 s,
-    clocks_triggered: [],
-    ..
-}

crates/fayalite/tests/sim/expected/connect_const_reset.txt

@@ -1,229 +0,0 @@
-Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 5,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
-                                ty: AsyncReset,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: AsyncReset,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                memories: StatePartLayout<Memories> {
-                    len: 0,
-                    debug_data: [],
-                    layout_data: [],
-                    ..
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:1:1
-                0: Const {
-                    dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    value: 0x1,
-                },
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
-                    src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                2: Copy {
-                    dest: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
-                    src: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:5:1
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
-                    src: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                5: Return,
-            ],
-            ..
-        },
-        pc: 5,
-        memory_write_log: [],
-        memories: StatePart {
-            value: [],
-        },
-        small_slots: StatePart {
-            value: [],
-        },
-        big_slots: StatePart {
-            value: [
-                1,
-                1,
-                1,
-                1,
-                1,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::connect_const_reset,
-        instantiated: Module {
-            name: connect_const_reset,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::connect_const_reset,
-            instantiated: Module {
-                name: connect_const_reset,
-                ..
-            },
-        }.bit_out: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::connect_const_reset,
-            instantiated: Module {
-                name: connect_const_reset,
-                ..
-            },
-        }.reset_out: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: AsyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
-                                ty: AsyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "connect_const_reset",
-        children: [
-            TraceModuleIO {
-                name: "reset_out",
-                child: TraceAsyncReset {
-                    location: TraceScalarId(0),
-                    name: "reset_out",
-                    flow: Sink,
-                },
-                ty: AsyncReset,
-                flow: Sink,
-            },
-            TraceModuleIO {
-                name: "bit_out",
-                child: TraceBool {
-                    location: TraceScalarId(1),
-                    name: "bit_out",
-                    flow: Sink,
-                },
-                ty: Bool,
-                flow: Sink,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigAsyncReset {
-                index: StatePartIndex<BigSlots>(0),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(1),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-    ],
-    trace_memories: {},
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 1 μs,
-    clocks_triggered: [],
-    ..
-}

crates/fayalite/tests/sim/expected/connect_const_reset.vcd

@@ -1,11 +0,0 @@
-$timescale 1 ps $end
-$scope module connect_const_reset $end
-$var wire 1 ! reset_out $end
-$var wire 1 " bit_out $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-1!
-1"
-$end
-#1000000

crates/fayalite/tests/sim/expected/counter_async.txt

@@ -1,522 +0,0 @@
-Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 4,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 10,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
-                                ty: AsyncReset,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count_reg",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count_reg$next",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<5>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                memories: StatePartLayout<Memories> {
-                    len: 0,
-                    debug_data: [],
-                    layout_data: [],
-                    ..
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:1:1
-                0: Const {
-                    dest: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    value: 0x1,
-                },
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                2: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                3: Const {
-                    dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
-                    value: 0x3,
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                4: BranchIfZero {
-                    target: 6,
-                    value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                5: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                6: Add {
-                    dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
-                    lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                7: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
-                    dest_width: 4,
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                8: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:6:1
-                9: Copy {
-                    dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                10: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
-                },
-                11: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                12: BranchIfSmallNonZero {
-                    target: 16,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                13: BranchIfSmallZero {
-                    target: 17,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                14: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                },
-                15: Branch {
-                    target: 17,
-                },
-                16: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                17: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                18: Return,
-            ],
-            ..
-        },
-        pc: 18,
-        memory_write_log: [],
-        memories: StatePart {
-            value: [],
-        },
-        small_slots: StatePart {
-            value: [
-                0,
-                0,
-                1,
-                0,
-            ],
-        },
-        big_slots: StatePart {
-            value: [
-                1,
-                0,
-                3,
-                3,
-                4,
-                3,
-                0,
-                1,
-                4,
-                4,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::counter,
-        instantiated: Module {
-            name: counter,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: AsyncReset,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
-                                ty: AsyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: AsyncReset,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: AsyncReset,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.rst: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: AsyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: AsyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.count: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "counter",
-        children: [
-            TraceModuleIO {
-                name: "cd",
-                child: TraceBundle {
-                    name: "cd",
-                    fields: [
-                        TraceClock {
-                            location: TraceScalarId(0),
-                            name: "clk",
-                            flow: Source,
-                        },
-                        TraceAsyncReset {
-                            location: TraceScalarId(1),
-                            name: "rst",
-                            flow: Source,
-                        },
-                    ],
-                    ty: Bundle {
-                        /* offset = 0 */
-                        clk: Clock,
-                        /* offset = 1 */
-                        rst: AsyncReset,
-                    },
-                    flow: Source,
-                },
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: AsyncReset,
-                },
-                flow: Source,
-            },
-            TraceModuleIO {
-                name: "count",
-                child: TraceUInt {
-                    location: TraceScalarId(2),
-                    name: "count",
-                    ty: UInt<4>,
-                    flow: Sink,
-                },
-                ty: UInt<4>,
-                flow: Sink,
-            },
-            TraceReg {
-                name: "count_reg",
-                child: TraceUInt {
-                    location: TraceScalarId(3),
-                    name: "count_reg",
-                    ty: UInt<4>,
-                    flow: Duplex,
-                },
-                ty: UInt<4>,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(0),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigAsyncReset {
-                index: StatePartIndex<BigSlots>(1),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(2),
-                ty: UInt<4>,
-            },
-            state: 0x3,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(3),
-                ty: UInt<4>,
-            },
-            state: 0x3,
-            last_state: 0x3,
-        },
-    ],
-    trace_memories: {},
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 66 μs,
-    clocks_triggered: [
-        StatePartIndex<SmallSlots>(1),
-    ],
-    ..
-}

crates/fayalite/tests/sim/expected/counter_async.vcd

@@ -1,217 +0,0 @@
-$timescale 1 ps $end
-$scope module counter $end
-$scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
-$upscope $end
-$var wire 4 # count $end
-$var reg 4 $ count_reg $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-0!
-0"
-b0 #
-b0 $
-$end
-#500000
-1"
-b11 #
-b11 $
-#1000000
-1!
-#1500000
-0"
-#2000000
-0!
-#3000000
-1!
-b100 $
-b100 #
-#4000000
-0!
-#5000000
-1!
-b101 $
-b101 #
-#6000000
-0!
-#7000000
-1!
-b110 $
-b110 #
-#8000000
-0!
-#9000000
-1!
-b111 $
-b111 #
-#10000000
-0!
-#11000000
-1!
-b1000 $
-b1000 #
-#12000000
-0!
-#13000000
-1!
-b1001 $
-b1001 #
-#14000000
-0!
-#15000000
-1!
-b1010 $
-b1010 #
-#16000000
-0!
-#17000000
-1!
-b1011 $
-b1011 #
-#18000000
-0!
-#19000000
-1!
-b1100 $
-b1100 #
-#20000000
-0!
-#21000000
-1!
-b1101 $
-b1101 #
-#22000000
-0!
-#23000000
-1!
-b1110 $
-b1110 #
-#24000000
-0!
-#25000000
-1!
-b1111 $
-b1111 #
-#26000000
-0!
-#27000000
-1!
-b0 $
-b0 #
-#28000000
-0!
-#29000000
-1!
-b1 $
-b1 #
-#30000000
-0!
-#31000000
-1!
-b10 $
-b10 #
-#32000000
-0!
-#33000000
-1!
-b11 $
-b11 #
-#34000000
-0!
-#35000000
-1!
-b100 $
-b100 #
-#36000000
-0!
-#37000000
-1!
-b101 $
-b101 #
-#38000000
-0!
-#39000000
-1!
-b110 $
-b110 #
-#40000000
-0!
-#41000000
-1!
-b111 $
-b111 #
-#42000000
-0!
-#43000000
-1!
-b1000 $
-b1000 #
-#44000000
-0!
-#45000000
-1!
-b1001 $
-b1001 #
-#46000000
-0!
-#47000000
-1!
-b1010 $
-b1010 #
-#48000000
-0!
-#49000000
-1!
-b1011 $
-b1011 #
-#50000000
-0!
-#51000000
-1!
-b1100 $
-b1100 #
-#52000000
-0!
-#53000000
-1!
-b1101 $
-b1101 #
-#54000000
-0!
-#55000000
-1!
-b1110 $
-b1110 #
-#56000000
-0!
-#57000000
-1!
-b1111 $
-b1111 #
-#58000000
-0!
-#59000000
-1!
-b0 $
-b0 #
-#60000000
-0!
-#61000000
-1!
-b1 $
-b1 #
-#62000000
-0!
-#63000000
-1!
-b10 $
-b10 #
-#64000000
-0!
-#65000000
-1!
-b11 $
-b11 #
-#66000000

crates/fayalite/tests/sim/expected/counter_sync.txt

@@ -1,503 +0,0 @@
-Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 4,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 9,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
-                                ty: SyncReset,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count_reg",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count_reg$next",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<5>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                memories: StatePartLayout<Memories> {
-                    len: 0,
-                    debug_data: [],
-                    layout_data: [],
-                    ..
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:6:1
-                0: Copy {
-                    dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                1: Const {
-                    dest: StatePartIndex<BigSlots>(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    value: 0x1,
-                },
-                2: Add {
-                    dest: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
-                    lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                3: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
-                    dest_width: 4,
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                5: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                6: Const {
-                    dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
-                    value: 0x3,
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                7: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
-                },
-                8: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                9: BranchIfSmallZero {
-                    target: 14,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                10: BranchIfSmallNonZero {
-                    target: 13,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                11: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                },
-                12: Branch {
-                    target: 14,
-                },
-                13: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                14: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                15: Return,
-            ],
-            ..
-        },
-        pc: 15,
-        memory_write_log: [],
-        memories: StatePart {
-            value: [],
-        },
-        small_slots: StatePart {
-            value: [
-                0,
-                0,
-                1,
-                0,
-            ],
-        },
-        big_slots: StatePart {
-            value: [
-                1,
-                0,
-                3,
-                3,
-                4,
-                3,
-                1,
-                4,
-                4,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::counter,
-        instantiated: Module {
-            name: counter,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SyncReset,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SyncReset,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.rst: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.count: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "counter",
-        children: [
-            TraceModuleIO {
-                name: "cd",
-                child: TraceBundle {
-                    name: "cd",
-                    fields: [
-                        TraceClock {
-                            location: TraceScalarId(0),
-                            name: "clk",
-                            flow: Source,
-                        },
-                        TraceSyncReset {
-                            location: TraceScalarId(1),
-                            name: "rst",
-                            flow: Source,
-                        },
-                    ],
-                    ty: Bundle {
-                        /* offset = 0 */
-                        clk: Clock,
-                        /* offset = 1 */
-                        rst: SyncReset,
-                    },
-                    flow: Source,
-                },
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
-                },
-                flow: Source,
-            },
-            TraceModuleIO {
-                name: "count",
-                child: TraceUInt {
-                    location: TraceScalarId(2),
-                    name: "count",
-                    ty: UInt<4>,
-                    flow: Sink,
-                },
-                ty: UInt<4>,
-                flow: Sink,
-            },
-            TraceReg {
-                name: "count_reg",
-                child: TraceUInt {
-                    location: TraceScalarId(3),
-                    name: "count_reg",
-                    ty: UInt<4>,
-                    flow: Duplex,
-                },
-                ty: UInt<4>,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(0),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigSyncReset {
-                index: StatePartIndex<BigSlots>(1),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(2),
-                ty: UInt<4>,
-            },
-            state: 0x3,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(3),
-                ty: UInt<4>,
-            },
-            state: 0x3,
-            last_state: 0x3,
-        },
-    ],
-    trace_memories: {},
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 66 μs,
-    clocks_triggered: [
-        StatePartIndex<SmallSlots>(1),
-    ],
-    ..
-}

crates/fayalite/tests/sim/expected/counter_sync.vcd

@@ -1,214 +0,0 @@
-$timescale 1 ps $end
-$scope module counter $end
-$scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
-$upscope $end
-$var wire 4 # count $end
-$var reg 4 $ count_reg $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-0!
-1"
-b0 #
-b0 $
-$end
-#1000000
-1!
-b11 $
-b11 #
-0"
-#2000000
-0!
-#3000000
-1!
-b100 $
-b100 #
-#4000000
-0!
-#5000000
-1!
-b101 $
-b101 #
-#6000000
-0!
-#7000000
-1!
-b110 $
-b110 #
-#8000000
-0!
-#9000000
-1!
-b111 $
-b111 #
-#10000000
-0!
-#11000000
-1!
-b1000 $
-b1000 #
-#12000000
-0!
-#13000000
-1!
-b1001 $
-b1001 #
-#14000000
-0!
-#15000000
-1!
-b1010 $
-b1010 #
-#16000000
-0!
-#17000000
-1!
-b1011 $
-b1011 #
-#18000000
-0!
-#19000000
-1!
-b1100 $
-b1100 #
-#20000000
-0!
-#21000000
-1!
-b1101 $
-b1101 #
-#22000000
-0!
-#23000000
-1!
-b1110 $
-b1110 #
-#24000000
-0!
-#25000000
-1!
-b1111 $
-b1111 #
-#26000000
-0!
-#27000000
-1!
-b0 $
-b0 #
-#28000000
-0!
-#29000000
-1!
-b1 $
-b1 #
-#30000000
-0!
-#31000000
-1!
-b10 $
-b10 #
-#32000000
-0!
-#33000000
-1!
-b11 $
-b11 #
-#34000000
-0!
-#35000000
-1!
-b100 $
-b100 #
-#36000000
-0!
-#37000000
-1!
-b101 $
-b101 #
-#38000000
-0!
-#39000000
-1!
-b110 $
-b110 #
-#40000000
-0!
-#41000000
-1!
-b111 $
-b111 #
-#42000000
-0!
-#43000000
-1!
-b1000 $
-b1000 #
-#44000000
-0!
-#45000000
-1!
-b1001 $
-b1001 #
-#46000000
-0!
-#47000000
-1!
-b1010 $
-b1010 #
-#48000000
-0!
-#49000000
-1!
-b1011 $
-b1011 #
-#50000000
-0!
-#51000000
-1!
-b1100 $
-b1100 #
-#52000000
-0!
-#53000000
-1!
-b1101 $
-b1101 #
-#54000000
-0!
-#55000000
-1!
-b1110 $
-b1110 #
-#56000000
-0!
-#57000000
-1!
-b1111 $
-b1111 #
-#58000000
-0!
-#59000000
-1!
-b0 $
-b0 #
-#60000000
-0!
-#61000000
-1!
-b1 $
-b1 #
-#62000000
-0!
-#63000000
-1!
-b10 $
-b10 #
-#64000000
-0!
-#65000000
-1!
-b11 $
-b11 #
-#66000000

crates/fayalite/tests/sim/expected/enums.vcd

@@ -1,110 +0,0 @@
-$timescale 1 ps $end
-$scope module enums $end
-$scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
-$upscope $end
-$var wire 1 # en $end
-$var wire 2 $ which_in $end
-$var wire 4 % data_in $end
-$var wire 2 & which_out $end
-$var wire 4 ' data_out $end
-$scope struct b_out $end
-$var string 1 ( \$tag $end
-$scope struct HdlSome $end
-$var wire 1 ) \0 $end
-$var wire 1 * \1 $end
-$upscope $end
-$upscope $end
-$scope struct the_reg $end
-$var string 1 + \$tag $end
-$scope struct B $end
-$var reg 1 , \0 $end
-$var reg 1 - \1 $end
-$upscope $end
-$scope struct C $end
-$scope struct a $end
-$var reg 1 . \[0] $end
-$var reg 1 / \[1] $end
-$upscope $end
-$var reg 2 0 b $end
-$upscope $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-0!
-1"
-0#
-b0 $
-b0 %
-b0 &
-b0 '
-sHdlNone\x20(0) (
-0)
-0*
-sA\x20(0) +
-0,
-0-
-0.
-0/
-b0 0
-$end
-#1000000
-1!
-#1100000
-0"
-#2000000
-0!
-#3000000
-1!
-#4000000
-1#
-b1 $
-0!
-#5000000
-1!
-b1 &
-sHdlSome\x20(1) (
-sB\x20(1) +
-#6000000
-0#
-b0 $
-0!
-#7000000
-1!
-#8000000
-1#
-b1 $
-b1111 %
-0!
-#9000000
-1!
-b11 '
-1)
-1*
-1,
-1-
-1.
-1/
-#10000000
-0!
-#11000000
-1!
-#12000000
-b10 $
-0!
-#13000000
-1!
-b10 &
-b1111 '
-sHdlNone\x20(0) (
-0)
-0*
-sC\x20(2) +
-b11 0
-#14000000
-0!
-#15000000
-1!
-#16000000

crates/fayalite/tests/sim/expected/memories.vcd

@@ -1,408 +0,0 @@
-$timescale 1 ps $end
-$scope module memories $end
-$scope struct r $end
-$var wire 4 ! addr $end
-$var wire 1 " en $end
-$var wire 1 # clk $end
-$scope struct data $end
-$var wire 8 $ \0 $end
-$var wire 8 % \1 $end
-$upscope $end
-$upscope $end
-$scope struct w $end
-$var wire 4 & addr $end
-$var wire 1 ' en $end
-$var wire 1 ( clk $end
-$scope struct data $end
-$var wire 8 ) \0 $end
-$var wire 8 * \1 $end
-$upscope $end
-$scope struct mask $end
-$var wire 1 + \0 $end
-$var wire 1 , \1 $end
-$upscope $end
-$upscope $end
-$scope struct mem $end
-$scope struct contents $end
-$scope struct [0] $end
-$scope struct mem $end
-$var reg 8 9 \0 $end
-$var reg 8 I \1 $end
-$upscope $end
-$upscope $end
-$scope struct [1] $end
-$scope struct mem $end
-$var reg 8 : \0 $end
-$var reg 8 J \1 $end
-$upscope $end
-$upscope $end
-$scope struct [2] $end
-$scope struct mem $end
-$var reg 8 ; \0 $end
-$var reg 8 K \1 $end
-$upscope $end
-$upscope $end
-$scope struct [3] $end
-$scope struct mem $end
-$var reg 8 < \0 $end
-$var reg 8 L \1 $end
-$upscope $end
-$upscope $end
-$scope struct [4] $end
-$scope struct mem $end
-$var reg 8 = \0 $end
-$var reg 8 M \1 $end
-$upscope $end
-$upscope $end
-$scope struct [5] $end
-$scope struct mem $end
-$var reg 8 > \0 $end
-$var reg 8 N \1 $end
-$upscope $end
-$upscope $end
-$scope struct [6] $end
-$scope struct mem $end
-$var reg 8 ? \0 $end
-$var reg 8 O \1 $end
-$upscope $end
-$upscope $end
-$scope struct [7] $end
-$scope struct mem $end
-$var reg 8 @ \0 $end
-$var reg 8 P \1 $end
-$upscope $end
-$upscope $end
-$scope struct [8] $end
-$scope struct mem $end
-$var reg 8 A \0 $end
-$var reg 8 Q \1 $end
-$upscope $end
-$upscope $end
-$scope struct [9] $end
-$scope struct mem $end
-$var reg 8 B \0 $end
-$var reg 8 R \1 $end
-$upscope $end
-$upscope $end
-$scope struct [10] $end
-$scope struct mem $end
-$var reg 8 C \0 $end
-$var reg 8 S \1 $end
-$upscope $end
-$upscope $end
-$scope struct [11] $end
-$scope struct mem $end
-$var reg 8 D \0 $end
-$var reg 8 T \1 $end
-$upscope $end
-$upscope $end
-$scope struct [12] $end
-$scope struct mem $end
-$var reg 8 E \0 $end
-$var reg 8 U \1 $end
-$upscope $end
-$upscope $end
-$scope struct [13] $end
-$scope struct mem $end
-$var reg 8 F \0 $end
-$var reg 8 V \1 $end
-$upscope $end
-$upscope $end
-$scope struct [14] $end
-$scope struct mem $end
-$var reg 8 G \0 $end
-$var reg 8 W \1 $end
-$upscope $end
-$upscope $end
-$scope struct [15] $end
-$scope struct mem $end
-$var reg 8 H \0 $end
-$var reg 8 X \1 $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct r0 $end
-$var wire 4 - addr $end
-$var wire 1 . en $end
-$var wire 1 / clk $end
-$scope struct data $end
-$var wire 8 0 \0 $end
-$var wire 8 1 \1 $end
-$upscope $end
-$upscope $end
-$scope struct w1 $end
-$var wire 4 2 addr $end
-$var wire 1 3 en $end
-$var wire 1 4 clk $end
-$scope struct data $end
-$var wire 8 5 \0 $end
-$var wire 8 6 \1 $end
-$upscope $end
-$scope struct mask $end
-$var wire 1 7 \0 $end
-$var wire 1 8 \1 $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-b1 9
-b100011 I
-b1 :
-b100011 J
-b1 ;
-b100011 K
-b1 <
-b100011 L
-b1 =
-b100011 M
-b1 >
-b100011 N
-b1 ?
-b100011 O
-b1 @
-b100011 P
-b1 A
-b100011 Q
-b1 B
-b100011 R
-b1 C
-b100011 S
-b1 D
-b100011 T
-b1 E
-b100011 U
-b1 F
-b100011 V
-b1 G
-b100011 W
-b1 H
-b100011 X
-b0 !
-0"
-0#
-b0 $
-b0 %
-b0 &
-0'
-0(
-b0 )
-b0 *
-0+
-0,
-b0 -
-0.
-0/
-b0 0
-b0 1
-b0 2
-03
-04
-b0 5
-b0 6
-07
-08
-$end
-#1000000
-1#
-1(
-1/
-14
-#2000000
-1"
-0#
-b1 $
-b100011 %
-1'
-0(
-b10000 )
-b100000 *
-1+
-1,
-1.
-0/
-b1 0
-b100011 1
-13
-04
-b10000 5
-b100000 6
-17
-18
-#3000000
-b10000 9
-b100000 I
-1#
-1(
-1/
-14
-b10000 $
-b100000 %
-b10000 0
-b100000 1
-#4000000
-0#
-0(
-b110000 )
-b1000000 *
-0+
-0/
-04
-b110000 5
-b1000000 6
-07
-#5000000
-b10000 9
-b1000000 I
-1#
-1(
-1/
-14
-b1000000 %
-b1000000 1
-#6000000
-0#
-0(
-b1010000 )
-b1100000 *
-1+
-0,
-0/
-04
-b1010000 5
-b1100000 6
-17
-08
-#7000000
-b1010000 9
-b1000000 I
-1#
-1(
-1/
-14
-b1010000 $
-b1010000 0
-#8000000
-0#
-0(
-b1110000 )
-b10000000 *
-0+
-0/
-04
-b1110000 5
-b10000000 6
-07
-#9000000
-1#
-1(
-1/
-14
-#10000000
-0#
-0'
-0(
-b10010000 )
-b10100000 *
-0/
-03
-04
-b10010000 5
-b10100000 6
-#11000000
-1#
-1(
-1/
-14
-#12000000
-0#
-b1 &
-1'
-0(
-1+
-1,
-0/
-b1 2
-13
-04
-17
-18
-#13000000
-b10010000 :
-b10100000 J
-1#
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-14
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-0#
-b10 &
-0(
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-04
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-b11000000 6
-#15000000
-b10110000 ;
-b11000000 K
-1#
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-14
-#16000000
-0#
-0'
-0(
-b11010000 )
-b11100000 *
-0/
-03
-04
-b11010000 5
-b11100000 6
-#17000000
-1#
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-b1 !
-0#
-b10010000 $
-b10100000 %
-0(
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-0/
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-04
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-b10 !
-0#
-b10110000 $
-b11000000 %
-0(
-b10 -
-0/
-b10110000 0
-b11000000 1
-04
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-1#
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-1/
-14
-#22000000
-0#
-0(
-0/
-04

crates/fayalite/tests/sim/expected/memories2.vcd

@@ -1,363 +0,0 @@
-$timescale 1 ps $end
-$scope module memories2 $end
-$scope struct rw $end
-$var wire 3 ! addr $end
-$var wire 1 " en $end
-$var wire 1 # clk $end
-$var wire 2 $ rdata $end
-$var wire 1 % wmode $end
-$var wire 2 & wdata $end
-$var wire 1 ' wmask $end
-$upscope $end
-$scope struct mem $end
-$scope struct contents $end
-$scope struct [0] $end
-$scope struct mem $end
-$var string 1 1 \$tag $end
-$var reg 1 6 HdlSome $end
-$upscope $end
-$upscope $end
-$scope struct [1] $end
-$scope struct mem $end
-$var string 1 2 \$tag $end
-$var reg 1 7 HdlSome $end
-$upscope $end
-$upscope $end
-$scope struct [2] $end
-$scope struct mem $end
-$var string 1 3 \$tag $end
-$var reg 1 8 HdlSome $end
-$upscope $end
-$upscope $end
-$scope struct [3] $end
-$scope struct mem $end
-$var string 1 4 \$tag $end
-$var reg 1 9 HdlSome $end
-$upscope $end
-$upscope $end
-$scope struct [4] $end
-$scope struct mem $end
-$var string 1 5 \$tag $end
-$var reg 1 : HdlSome $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct rw0 $end
-$var wire 3 ( addr $end
-$var wire 1 ) en $end
-$var wire 1 * clk $end
-$scope struct rdata $end
-$var string 1 + \$tag $end
-$var wire 1 , HdlSome $end
-$upscope $end
-$var wire 1 - wmode $end
-$scope struct wdata $end
-$var string 1 . \$tag $end
-$var wire 1 / HdlSome $end
-$upscope $end
-$var wire 1 0 wmask $end
-$upscope $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-sHdlSome\x20(1) 1
-16
-sHdlSome\x20(1) 2
-17
-sHdlSome\x20(1) 3
-18
-sHdlSome\x20(1) 4
-19
-sHdlSome\x20(1) 5
-1:
-b0 !
-0"
-0#
-b0 $
-0%
-b0 &
-0'
-b0 (
-0)
-0*
-sHdlNone\x20(0) +
-0,
-0-
-sHdlNone\x20(0) .
-0/
-00
-$end
-#250000
-1#
-1*
-#500000
-#750000
-0#
-0*
-#1000000
-1"
-1)
-#1250000
-1#
-1*
-b11 $
-sHdlSome\x20(1) +
-1,
-#1500000
-#1750000
-0#
-0*
-#2000000
-0"
-0)
-#2250000
-1#
-1*
-b0 $
-sHdlNone\x20(0) +
-0,
-#2500000
-#2750000
-0#
-0*
-#3000000
-1"
-1%
-1'
-1)
-1-
-10
-#3250000
-sHdlNone\x20(0) 1
-06
-1#
-1*
-#3500000
-#3750000
-0#
-0*
-#4000000
-0%
-0'
-0-
-00
-#4250000
-1#
-1*
-#4500000
-#4750000
-0#
-0*
-#5000000
-1%
-b11 &
-1-
-sHdlSome\x20(1) .
-1/
-#5250000
-1#
-1*
-#5500000
-#5750000
-0#
-0*
-#6000000
-b1 !
-b1 &
-1'
-b1 (
-0/
-10
-#6250000
-sHdlSome\x20(1) 2
-07
-1#
-1*
-#6500000
-#6750000
-0#
-0*
-#7000000
-b10 !
-b10 &
-b10 (
-sHdlNone\x20(0) .
-#7250000
-sHdlNone\x20(0) 3
-08
-1#
-1*
-#7500000
-#7750000
-0#
-0*
-#8000000
-b11 !
-b11 &
-b11 (
-sHdlSome\x20(1) .
-1/
-#8250000
-sHdlSome\x20(1) 4
-19
-1#
-1*
-#8500000
-#8750000
-0#
-0*
-#9000000
-b100 !
-b10 &
-b100 (
-sHdlNone\x20(0) .
-0/
-#9250000
-sHdlNone\x20(0) 5
-0:
-1#
-1*
-#9500000
-#9750000
-0#
-0*
-#10000000
-b101 !
-b1 &
-b101 (
-sHdlSome\x20(1) .
-#10250000
-1#
-1*
-#10500000
-#10750000
-0#
-0*
-#11000000
-b110 !
-b110 (
-#11250000
-1#
-1*
-#11500000
-#11750000
-0#
-0*
-#12000000
-b111 !
-b111 (
-#12250000
-1#
-1*
-#12500000
-#12750000
-0#
-0*
-#13000000
-0%
-b0 &
-0'
-0-
-sHdlNone\x20(0) .
-00
-#13250000
-1#
-1*
-#13500000
-#13750000
-0#
-0*
-#14000000
-b110 !
-b110 (
-#14250000
-1#
-1*
-#14500000
-#14750000
-0#
-0*
-#15000000
-b101 !
-b101 (
-#15250000
-1#
-1*
-#15500000
-#15750000
-0#
-0*
-#16000000
-b100 !
-b100 (
-#16250000
-1#
-1*
-#16500000
-#16750000
-0#
-0*
-#17000000
-b11 !
-b11 (
-#17250000
-1#
-1*
-b11 $
-sHdlSome\x20(1) +
-1,
-#17500000
-#17750000
-0#
-0*
-#18000000
-b10 !
-b10 (
-#18250000
-1#
-1*
-b0 $
-sHdlNone\x20(0) +
-0,
-#18500000
-#18750000
-0#
-0*
-#19000000
-b0 !
-b0 (
-#19250000
-1#
-1*
-#19500000
-#19750000
-0#
-0*
-#20000000
-b1 !
-b1 (
-#20250000
-1#
-1*
-b1 $
-sHdlSome\x20(1) +
-#20500000
-#20750000
-0#
-0*
-#21000000
-b0 !
-0"
-b0 (
-0)
-#21250000
-1#
-1*
-b0 $
-sHdlNone\x20(0) +
-#21500000
-#21750000
-0#
-0*
-#22000000

crates/fayalite/tests/sim/expected/memories3.vcd

@@ -1,836 +0,0 @@
-$timescale 1 ps $end
-$scope module memories3 $end
-$scope struct r $end
-$var wire 3 ! addr $end
-$var wire 1 " en $end
-$var wire 1 # clk $end
-$scope struct data $end
-$var wire 8 $ \[0] $end
-$var wire 8 % \[1] $end
-$var wire 8 & \[2] $end
-$var wire 8 ' \[3] $end
-$var wire 8 ( \[4] $end
-$var wire 8 ) \[5] $end
-$var wire 8 * \[6] $end
-$var wire 8 + \[7] $end
-$upscope $end
-$upscope $end
-$scope struct w $end
-$var wire 3 , addr $end
-$var wire 1 - en $end
-$var wire 1 . clk $end
-$scope struct data $end
-$var wire 8 / \[0] $end
-$var wire 8 0 \[1] $end
-$var wire 8 1 \[2] $end
-$var wire 8 2 \[3] $end
-$var wire 8 3 \[4] $end
-$var wire 8 4 \[5] $end
-$var wire 8 5 \[6] $end
-$var wire 8 6 \[7] $end
-$upscope $end
-$scope struct mask $end
-$var wire 1 7 \[0] $end
-$var wire 1 8 \[1] $end
-$var wire 1 9 \[2] $end
-$var wire 1 : \[3] $end
-$var wire 1 ; \[4] $end
-$var wire 1 < \[5] $end
-$var wire 1 = \[6] $end
-$var wire 1 > \[7] $end
-$upscope $end
-$upscope $end
-$scope struct mem $end
-$scope struct contents $end
-$scope struct [0] $end
-$scope struct mem $end
-$var reg 8 ] \[0] $end
-$var reg 8 e \[1] $end
-$var reg 8 m \[2] $end
-$var reg 8 u \[3] $end
-$var reg 8 } \[4] $end
-$var reg 8 '" \[5] $end
-$var reg 8 /" \[6] $end
-$var reg 8 7" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [1] $end
-$scope struct mem $end
-$var reg 8 ^ \[0] $end
-$var reg 8 f \[1] $end
-$var reg 8 n \[2] $end
-$var reg 8 v \[3] $end
-$var reg 8 ~ \[4] $end
-$var reg 8 (" \[5] $end
-$var reg 8 0" \[6] $end
-$var reg 8 8" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [2] $end
-$scope struct mem $end
-$var reg 8 _ \[0] $end
-$var reg 8 g \[1] $end
-$var reg 8 o \[2] $end
-$var reg 8 w \[3] $end
-$var reg 8 !" \[4] $end
-$var reg 8 )" \[5] $end
-$var reg 8 1" \[6] $end
-$var reg 8 9" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [3] $end
-$scope struct mem $end
-$var reg 8 ` \[0] $end
-$var reg 8 h \[1] $end
-$var reg 8 p \[2] $end
-$var reg 8 x \[3] $end
-$var reg 8 "" \[4] $end
-$var reg 8 *" \[5] $end
-$var reg 8 2" \[6] $end
-$var reg 8 :" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [4] $end
-$scope struct mem $end
-$var reg 8 a \[0] $end
-$var reg 8 i \[1] $end
-$var reg 8 q \[2] $end
-$var reg 8 y \[3] $end
-$var reg 8 #" \[4] $end
-$var reg 8 +" \[5] $end
-$var reg 8 3" \[6] $end
-$var reg 8 ;" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [5] $end
-$scope struct mem $end
-$var reg 8 b \[0] $end
-$var reg 8 j \[1] $end
-$var reg 8 r \[2] $end
-$var reg 8 z \[3] $end
-$var reg 8 $" \[4] $end
-$var reg 8 ," \[5] $end
-$var reg 8 4" \[6] $end
-$var reg 8 <" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [6] $end
-$scope struct mem $end
-$var reg 8 c \[0] $end
-$var reg 8 k \[1] $end
-$var reg 8 s \[2] $end
-$var reg 8 { \[3] $end
-$var reg 8 %" \[4] $end
-$var reg 8 -" \[5] $end
-$var reg 8 5" \[6] $end
-$var reg 8 =" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [7] $end
-$scope struct mem $end
-$var reg 8 d \[0] $end
-$var reg 8 l \[1] $end
-$var reg 8 t \[2] $end
-$var reg 8 | \[3] $end
-$var reg 8 &" \[4] $end
-$var reg 8 ." \[5] $end
-$var reg 8 6" \[6] $end
-$var reg 8 >" \[7] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct r0 $end
-$var wire 3 ? addr $end
-$var wire 1 @ en $end
-$var wire 1 A clk $end
-$scope struct data $end
-$var wire 8 B \[0] $end
-$var wire 8 C \[1] $end
-$var wire 8 D \[2] $end
-$var wire 8 E \[3] $end
-$var wire 8 F \[4] $end
-$var wire 8 G \[5] $end
-$var wire 8 H \[6] $end
-$var wire 8 I \[7] $end
-$upscope $end
-$upscope $end
-$scope struct w1 $end
-$var wire 3 J addr $end
-$var wire 1 K en $end
-$var wire 1 L clk $end
-$scope struct data $end
-$var wire 8 M \[0] $end
-$var wire 8 N \[1] $end
-$var wire 8 O \[2] $end
-$var wire 8 P \[3] $end
-$var wire 8 Q \[4] $end
-$var wire 8 R \[5] $end
-$var wire 8 S \[6] $end
-$var wire 8 T \[7] $end
-$upscope $end
-$scope struct mask $end
-$var wire 1 U \[0] $end
-$var wire 1 V \[1] $end
-$var wire 1 W \[2] $end
-$var wire 1 X \[3] $end
-$var wire 1 Y \[4] $end
-$var wire 1 Z \[5] $end
-$var wire 1 [ \[6] $end
-$var wire 1 \ \[7] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-b0 ]
-b0 e
-b0 m
-b0 u
-b0 }
-b0 '"
-b0 /"
-b0 7"
-b0 ^
-b0 f
-b0 n
-b0 v
-b0 ~
-b0 ("
-b0 0"
-b0 8"
-b0 _
-b0 g
-b0 o
-b0 w
-b0 !"
-b0 )"
-b0 1"
-b0 9"
-b0 `
-b0 h
-b0 p
-b0 x
-b0 ""
-b0 *"
-b0 2"
-b0 :"
-b0 a
-b0 i
-b0 q
-b0 y
-b0 #"
-b0 +"
-b0 3"
-b0 ;"
-b0 b
-b0 j
-b0 r
-b0 z
-b0 $"
-b0 ,"
-b0 4"
-b0 <"
-b0 c
-b0 k
-b0 s
-b0 {
-b0 %"
-b0 -"
-b0 5"
-b0 ="
-b0 d
-b0 l
-b0 t
-b0 |
-b0 &"
-b0 ."
-b0 6"
-b0 >"
-b0 !
-0"
-0#
-b0 $
-b0 %
-b0 &
-b0 '
-b0 (
-b0 )
-b0 *
-b0 +
-b0 ,
-1-
-0.
-b10010 /
-b110100 0
-b1010110 1
-b1111000 2
-b10011010 3
-b10111100 4
-b11011110 5
-b11110000 6
-07
-18
-09
-1:
-1;
-0<
-0=
-1>
-b0 ?
-0@
-0A
-b0 B
-b0 C
-b0 D
-b0 E
-b0 F
-b0 G
-b0 H
-b0 I
-b0 J
-1K
-0L
-b10010 M
-b110100 N
-b1010110 O
-b1111000 P
-b10011010 Q
-b10111100 R
-b11011110 S
-b11110000 T
-0U
-1V
-0W
-1X
-1Y
-0Z
-0[
-1\
-$end
-#250000
-1#
-1.
-1A
-1L
-#500000
-#750000
-0#
-0.
-0A
-0L
-#1000000
-1"
-b1 ,
-0-
-b0 /
-b0 0
-b0 1
-b0 2
-b0 3
-b0 4
-b0 5
-b0 6
-08
-0:
-0;
-0>
-1@
-b1 J
-0K
-b0 M
-b0 N
-b0 O
-b0 P
-b0 Q
-b0 R
-b0 S
-b0 T
-0V
-0X
-0Y
-0\
-#1250000
-b0 ]
-b110100 e
-b0 m
-b1111000 u
-b10011010 }
-b0 '"
-b0 /"
-b11110000 7"
-1#
-1.
-1A
-1L
-#1500000
-#1750000
-0#
-0.
-0A
-0L
-#2000000
-#2250000
-1#
-1.
-1A
-1L
-#2500000
-#2750000
-0#
-0.
-0A
-0L
-#3000000
-b0 ,
-1-
-b11111110 /
-b11011100 0
-b10111010 1
-b10011000 2
-b1110110 3
-b1010100 4
-b110010 5
-b10000 6
-17
-18
-19
-1:
-1;
-1<
-1=
-1>
-b0 J
-1K
-b11111110 M
-b11011100 N
-b10111010 O
-b10011000 P
-b1110110 Q
-b1010100 R
-b110010 S
-b10000 T
-1U
-1V
-1W
-1X
-1Y
-1Z
-1[
-1\
-#3250000
-1#
-1.
-1A
-b110100 C
-b1111000 E
-b10011010 F
-b11110000 I
-1L
-b110100 %
-b1111000 '
-b10011010 (
-b11110000 +
-#3500000
-#3750000
-0#
-0.
-0A
-0L
-#4000000
-#4250000
-b11111110 ]
-b11011100 e
-b10111010 m
-b10011000 u
-b1110110 }
-b1010100 '"
-b110010 /"
-b10000 7"
-1#
-1.
-1A
-1L
-#4500000
-#4750000
-0#
-0.
-0A
-0L
-#5000000
-#5250000
-b11111110 ]
-b11011100 e
-b10111010 m
-b10011000 u
-b1110110 }
-b1010100 '"
-b110010 /"
-b10000 7"
-1#
-1.
-1A
-1L
-#5500000
-#5750000
-0#
-0.
-0A
-0L
-#6000000
-0"
-b1 ,
-b10011 /
-b1010111 0
-b10011011 1
-b11011111 2
-b10 3
-b1000110 4
-b10001010 5
-b11001110 6
-0@
-b1 J
-b10011 M
-b1010111 N
-b10011011 O
-b11011111 P
-b10 Q
-b1000110 R
-b10001010 S
-b11001110 T
-#6250000
-b11111110 ]
-b11011100 e
-b10111010 m
-b10011000 u
-b1110110 }
-b1010100 '"
-b110010 /"
-b10000 7"
-1#
-1.
-1A
-b11111110 B
-b11011100 C
-b10111010 D
-b10011000 E
-b1110110 F
-b1010100 G
-b110010 H
-b10000 I
-1L
-b11111110 $
-b11011100 %
-b10111010 &
-b10011000 '
-b1110110 (
-b1010100 )
-b110010 *
-b10000 +
-#6500000
-#6750000
-0#
-0.
-0A
-0L
-#7000000
-b10 ,
-b1110100 /
-b1100101 0
-b1110011 1
-b1110100 2
-b1101001 3
-b1101110 4
-b1100111 5
-b100001 6
-b10 J
-b1110100 M
-b1100101 N
-b1110011 O
-b1110100 P
-b1101001 Q
-b1101110 R
-b1100111 S
-b100001 T
-#7250000
-b10011 ^
-b1010111 f
-b10011011 n
-b11011111 v
-b10 ~
-b1000110 ("
-b10001010 0"
-b11001110 8"
-1#
-1.
-1A
-b0 B
-b0 C
-b0 D
-b0 E
-b0 F
-b0 G
-b0 H
-b0 I
-1L
-b0 $
-b0 %
-b0 &
-b0 '
-b0 (
-b0 )
-b0 *
-b0 +
-#7500000
-#7750000
-0#
-0.
-0A
-0L
-#8000000
-b11 ,
-b1101101 /
-b1101111 0
-b1110010 1
-b1100101 2
-b100000 3
-b1110100 4
-b1110011 5
-b1110100 6
-b11 J
-b1101101 M
-b1101111 N
-b1110010 O
-b1100101 P
-b100000 Q
-b1110100 R
-b1110011 S
-b1110100 T
-#8250000
-b1110100 _
-b1100101 g
-b1110011 o
-b1110100 w
-b1101001 !"
-b1101110 )"
-b1100111 1"
-b100001 9"
-1#
-1.
-1A
-1L
-#8500000
-#8750000
-0#
-0.
-0A
-0L
-#9000000
-1"
-b0 ,
-0-
-b0 /
-b0 0
-b0 1
-b0 2
-b0 3
-b0 4
-b0 5
-b0 6
-07
-08
-09
-0:
-0;
-0<
-0=
-0>
-1@
-b0 J
-0K
-b0 M
-b0 N
-b0 O
-b0 P
-b0 Q
-b0 R
-b0 S
-b0 T
-0U
-0V
-0W
-0X
-0Y
-0Z
-0[
-0\
-#9250000
-b1101101 `
-b1101111 h
-b1110010 p
-b1100101 x
-b100000 ""
-b1110100 *"
-b1110011 2"
-b1110100 :"
-1#
-1.
-1A
-1L
-#9500000
-#9750000
-0#
-0.
-0A
-0L
-#10000000
-b1 !
-b1 ?
-#10250000
-1#
-1.
-1A
-b11111110 B
-b11011100 C
-b10111010 D
-b10011000 E
-b1110110 F
-b1010100 G
-b110010 H
-b10000 I
-1L
-b11111110 $
-b11011100 %
-b10111010 &
-b10011000 '
-b1110110 (
-b1010100 )
-b110010 *
-b10000 +
-#10500000
-#10750000
-0#
-0.
-0A
-0L
-#11000000
-b10 !
-b10 ?
-#11250000
-1#
-1.
-1A
-b10011 B
-b1010111 C
-b10011011 D
-b11011111 E
-b10 F
-b1000110 G
-b10001010 H
-b11001110 I
-1L
-b10011 $
-b1010111 %
-b10011011 &
-b11011111 '
-b10 (
-b1000110 )
-b10001010 *
-b11001110 +
-#11500000
-#11750000
-0#
-0.
-0A
-0L
-#12000000
-b11 !
-b11 ?
-#12250000
-1#
-1.
-1A
-b1110100 B
-b1100101 C
-b1110011 D
-b1110100 E
-b1101001 F
-b1101110 G
-b1100111 H
-b100001 I
-1L
-b1110100 $
-b1100101 %
-b1110011 &
-b1110100 '
-b1101001 (
-b1101110 )
-b1100111 *
-b100001 +
-#12500000
-#12750000
-0#
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-#13000000
-b0 !
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-0@
-#13250000
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-1.
-1A
-b1101101 B
-b1101111 C
-b1110010 D
-b1100101 E
-b100000 F
-b1110100 G
-b1110011 H
-b1110100 I
-1L
-b1101101 $
-b1101111 %
-b1110010 &
-b1100101 '
-b100000 (
-b1110100 )
-b1110011 *
-b1110100 +
-#13500000
-#13750000
-0#
-0.
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-#14250000
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-1.
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-b0 C
-b0 D
-b0 E
-b0 F
-b0 G
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-#14500000
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-#15000000

crates/fayalite/tests/sim/expected/mod1.txt

@@ -1,810 +0,0 @@
-Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 17,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.i",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.o",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::child.i",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::child.o",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::child.i2",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::child.o2",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                memories: StatePartLayout<Memories> {
-                    len: 0,
-                    debug_data: [],
-                    layout_data: [],
-                    ..
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:4:1
-                0: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(2), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
-                },
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(0), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:2:1
-                2: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
-                },
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX-2.rs:1:1
-                4: Const {
-                    dest: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    value: 0xf,
-                },
-                5: Const {
-                    dest: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
-                    value: 0x5,
-                },
-                6: CmpLt {
-                    dest: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
-                },
-                7: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
-                    dest_width: 4,
-                },
-                // at: module-XXXXXXXXXX-2.rs:7:1
-                8: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX-2.rs:8:1
-                9: BranchIfZero {
-                    target: 11,
-                    value: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX-2.rs:9:1
-                10: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:2:1
-                11: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                12: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX-2.rs:1:1
-                13: CastToSInt {
-                    dest: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
-                    dest_width: 2,
-                },
-                // at: module-XXXXXXXXXX-2.rs:6:1
-                14: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:2:1
-                15: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                16: Copy {
-                    dest: StatePartIndex<BigSlots>(1), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                17: Return,
-            ],
-            ..
-        },
-        pc: 17,
-        memory_write_log: [],
-        memories: StatePart {
-            value: [],
-        },
-        small_slots: StatePart {
-            value: [],
-        },
-        big_slots: StatePart {
-            value: [
-                10,
-                -2,
-                -2,
-                15,
-                10,
-                -2,
-                -2,
-                15,
-                10,
-                -2,
-                -2,
-                15,
-                -2,
-                14,
-                5,
-                1,
-                15,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::mod1,
-        instantiated: Module {
-            name: mod1,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    #[hdl(flip)] /* offset = 0 */
-                    i: UInt<4>,
-                    /* offset = 4 */
-                    o: SInt<2>,
-                    #[hdl(flip)] /* offset = 6 */
-                    i2: SInt<2>,
-                    /* offset = 8 */
-                    o2: UInt<4>,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 4,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.i",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.o",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<4>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<4>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SInt<2>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SInt<2>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(2),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SInt<2>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SInt<2>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(3),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<4>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<4>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.i: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.i2: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.o: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.o2: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "mod1",
-        children: [
-            TraceModuleIO {
-                name: "o",
-                child: TraceBundle {
-                    name: "o",
-                    fields: [
-                        TraceUInt {
-                            location: TraceScalarId(0),
-                            name: "i",
-                            ty: UInt<4>,
-                            flow: Source,
-                        },
-                        TraceSInt {
-                            location: TraceScalarId(1),
-                            name: "o",
-                            ty: SInt<2>,
-                            flow: Sink,
-                        },
-                        TraceSInt {
-                            location: TraceScalarId(2),
-                            name: "i2",
-                            ty: SInt<2>,
-                            flow: Source,
-                        },
-                        TraceUInt {
-                            location: TraceScalarId(3),
-                            name: "o2",
-                            ty: UInt<4>,
-                            flow: Sink,
-                        },
-                    ],
-                    ty: Bundle {
-                        #[hdl(flip)] /* offset = 0 */
-                        i: UInt<4>,
-                        /* offset = 4 */
-                        o: SInt<2>,
-                        #[hdl(flip)] /* offset = 6 */
-                        i2: SInt<2>,
-                        /* offset = 8 */
-                        o2: UInt<4>,
-                    },
-                    flow: Sink,
-                },
-                ty: Bundle {
-                    #[hdl(flip)] /* offset = 0 */
-                    i: UInt<4>,
-                    /* offset = 4 */
-                    o: SInt<2>,
-                    #[hdl(flip)] /* offset = 6 */
-                    i2: SInt<2>,
-                    /* offset = 8 */
-                    o2: UInt<4>,
-                },
-                flow: Sink,
-            },
-            TraceInstance {
-                name: "child",
-                instance_io: TraceBundle {
-                    name: "child",
-                    fields: [
-                        TraceUInt {
-                            location: TraceScalarId(8),
-                            name: "i",
-                            ty: UInt<4>,
-                            flow: Sink,
-                        },
-                        TraceSInt {
-                            location: TraceScalarId(9),
-                            name: "o",
-                            ty: SInt<2>,
-                            flow: Source,
-                        },
-                        TraceSInt {
-                            location: TraceScalarId(10),
-                            name: "i2",
-                            ty: SInt<2>,
-                            flow: Sink,
-                        },
-                        TraceUInt {
-                            location: TraceScalarId(11),
-                            name: "o2",
-                            ty: UInt<4>,
-                            flow: Source,
-                        },
-                    ],
-                    ty: Bundle {
-                        #[hdl(flip)] /* offset = 0 */
-                        i: UInt<4>,
-                        /* offset = 4 */
-                        o: SInt<2>,
-                        #[hdl(flip)] /* offset = 6 */
-                        i2: SInt<2>,
-                        /* offset = 8 */
-                        o2: UInt<4>,
-                    },
-                    flow: Source,
-                },
-                module: TraceModule {
-                    name: "mod1_child",
-                    children: [
-                        TraceModuleIO {
-                            name: "i",
-                            child: TraceUInt {
-                                location: TraceScalarId(4),
-                                name: "i",
-                                ty: UInt<4>,
-                                flow: Source,
-                            },
-                            ty: UInt<4>,
-                            flow: Source,
-                        },
-                        TraceModuleIO {
-                            name: "o",
-                            child: TraceSInt {
-                                location: TraceScalarId(5),
-                                name: "o",
-                                ty: SInt<2>,
-                                flow: Sink,
-                            },
-                            ty: SInt<2>,
-                            flow: Sink,
-                        },
-                        TraceModuleIO {
-                            name: "i2",
-                            child: TraceSInt {
-                                location: TraceScalarId(6),
-                                name: "i2",
-                                ty: SInt<2>,
-                                flow: Source,
-                            },
-                            ty: SInt<2>,
-                            flow: Source,
-                        },
-                        TraceModuleIO {
-                            name: "o2",
-                            child: TraceUInt {
-                                location: TraceScalarId(7),
-                                name: "o2",
-                                ty: UInt<4>,
-                                flow: Sink,
-                            },
-                            ty: UInt<4>,
-                            flow: Sink,
-                        },
-                    ],
-                },
-                ty: Bundle {
-                    #[hdl(flip)] /* offset = 0 */
-                    i: UInt<4>,
-                    /* offset = 4 */
-                    o: SInt<2>,
-                    #[hdl(flip)] /* offset = 6 */
-                    i2: SInt<2>,
-                    /* offset = 8 */
-                    o2: UInt<4>,
-                },
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(0),
-                ty: UInt<4>,
-            },
-            state: 0xa,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(1),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(2),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(3),
-                ty: UInt<4>,
-            },
-            state: 0xf,
-            last_state: 0xe,
-        },
-        SimTrace {
-            id: TraceScalarId(4),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(8),
-                ty: UInt<4>,
-            },
-            state: 0xa,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(5),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(9),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(6),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(10),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(7),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(11),
-                ty: UInt<4>,
-            },
-            state: 0xf,
-            last_state: 0xe,
-        },
-        SimTrace {
-            id: TraceScalarId(8),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(4),
-                ty: UInt<4>,
-            },
-            state: 0xa,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(9),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(5),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(10),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(6),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(11),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(7),
-                ty: UInt<4>,
-            },
-            state: 0xf,
-            last_state: 0xe,
-        },
-    ],
-    trace_memories: {},
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 2 μs,
-    clocks_triggered: [],
-    ..
-}

crates/fayalite/tests/sim/expected/mod1.vcd

@@ -1,47 +0,0 @@
-$timescale 1 ps $end
-$scope module mod1 $end
-$scope struct o $end
-$var wire 4 ! i $end
-$var wire 2 " o $end
-$var wire 2 # i2 $end
-$var wire 4 $ o2 $end
-$upscope $end
-$scope struct child $end
-$var wire 4 ) i $end
-$var wire 2 * o $end
-$var wire 2 + i2 $end
-$var wire 4 , o2 $end
-$upscope $end
-$scope module mod1_child $end
-$var wire 4 % i $end
-$var wire 2 & o $end
-$var wire 2 ' i2 $end
-$var wire 4 ( o2 $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-b11 !
-b11 "
-b10 #
-b1110 $
-b11 %
-b11 &
-b10 '
-b1110 (
-b11 )
-b11 *
-b10 +
-b1110 ,
-$end
-#1000000
-b1010 !
-b10 "
-b1111 $
-b1010 %
-b10 &
-b1111 (
-b1010 )
-b10 *
-b1111 ,
-#2000000

crates/fayalite/tests/sim/expected/shift_register.txt

@@ -1,683 +0,0 @@
-Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 4,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 13,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
-                                ty: SyncReset,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                memories: StatePartLayout<Memories> {
-                    len: 0,
-                    debug_data: [],
-                    layout_data: [],
-                    ..
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:13:1
-                0: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
-                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:10:1
-                2: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:8:1
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:6:1
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:5:1
-                5: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                6: Const {
-                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    value: 0x0,
-                },
-                // at: module-XXXXXXXXXX.rs:5:1
-                7: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
-                },
-                8: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                9: BranchIfSmallZero {
-                    target: 14,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                10: BranchIfSmallNonZero {
-                    target: 13,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                11: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
-                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
-                },
-                12: Branch {
-                    target: 14,
-                },
-                13: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:7:1
-                14: BranchIfSmallZero {
-                    target: 19,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                15: BranchIfSmallNonZero {
-                    target: 18,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                16: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
-                },
-                17: Branch {
-                    target: 19,
-                },
-                18: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:9:1
-                19: BranchIfSmallZero {
-                    target: 24,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                20: BranchIfSmallNonZero {
-                    target: 23,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                21: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
-                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
-                },
-                22: Branch {
-                    target: 24,
-                },
-                23: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:11:1
-                24: BranchIfSmallZero {
-                    target: 29,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                25: BranchIfSmallNonZero {
-                    target: 28,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                26: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
-                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
-                },
-                27: Branch {
-                    target: 29,
-                },
-                28: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:5:1
-                29: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                30: Return,
-            ],
-            ..
-        },
-        pc: 30,
-        memory_write_log: [],
-        memories: StatePart {
-            value: [],
-        },
-        small_slots: StatePart {
-            value: [
-                0,
-                0,
-                1,
-                0,
-            ],
-        },
-        big_slots: StatePart {
-            value: [
-                1,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::shift_register,
-        instantiated: Module {
-            name: shift_register,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.cd: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SyncReset,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SyncReset,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.cd.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.cd.rst: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.d: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.q: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "shift_register",
-        children: [
-            TraceModuleIO {
-                name: "cd",
-                child: TraceBundle {
-                    name: "cd",
-                    fields: [
-                        TraceClock {
-                            location: TraceScalarId(0),
-                            name: "clk",
-                            flow: Source,
-                        },
-                        TraceSyncReset {
-                            location: TraceScalarId(1),
-                            name: "rst",
-                            flow: Source,
-                        },
-                    ],
-                    ty: Bundle {
-                        /* offset = 0 */
-                        clk: Clock,
-                        /* offset = 1 */
-                        rst: SyncReset,
-                    },
-                    flow: Source,
-                },
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
-                },
-                flow: Source,
-            },
-            TraceModuleIO {
-                name: "d",
-                child: TraceBool {
-                    location: TraceScalarId(2),
-                    name: "d",
-                    flow: Source,
-                },
-                ty: Bool,
-                flow: Source,
-            },
-            TraceModuleIO {
-                name: "q",
-                child: TraceBool {
-                    location: TraceScalarId(3),
-                    name: "q",
-                    flow: Sink,
-                },
-                ty: Bool,
-                flow: Sink,
-            },
-            TraceReg {
-                name: "reg0",
-                child: TraceBool {
-                    location: TraceScalarId(4),
-                    name: "reg0",
-                    flow: Duplex,
-                },
-                ty: Bool,
-            },
-            TraceReg {
-                name: "reg1",
-                child: TraceBool {
-                    location: TraceScalarId(5),
-                    name: "reg1",
-                    flow: Duplex,
-                },
-                ty: Bool,
-            },
-            TraceReg {
-                name: "reg2",
-                child: TraceBool {
-                    location: TraceScalarId(6),
-                    name: "reg2",
-                    flow: Duplex,
-                },
-                ty: Bool,
-            },
-            TraceReg {
-                name: "reg3",
-                child: TraceBool {
-                    location: TraceScalarId(7),
-                    name: "reg3",
-                    flow: Duplex,
-                },
-                ty: Bool,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(0),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigSyncReset {
-                index: StatePartIndex<BigSlots>(1),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(2),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(3),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(4),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(4),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(5),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(7),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(6),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(9),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(7),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(11),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-    ],
-    trace_memories: {},
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 66 μs,
-    clocks_triggered: [
-        StatePartIndex<SmallSlots>(1),
-    ],
-    ..
-}

crates/fayalite/tests/sim/expected/shift_register.vcd

@@ -1,193 +0,0 @@
-$timescale 1 ps $end
-$scope module shift_register $end
-$scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
-$upscope $end
-$var wire 1 # d $end
-$var wire 1 $ q $end
-$var reg 1 % reg0 $end
-$var reg 1 & reg1 $end
-$var reg 1 ' reg2 $end
-$var reg 1 ( reg3 $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-0!
-1"
-0#
-0$
-0%
-0&
-0'
-0(
-$end
-#1000000
-1!
-#1100000
-0"
-#2000000
-0!
-#3000000
-1!
-#4000000
-0!
-1#
-#5000000
-1!
-1%
-#6000000
-0!
-#7000000
-1!
-1&
-#8000000
-0!
-0#
-#9000000
-1!
-0%
-1'
-#10000000
-0!
-#11000000
-1!
-0&
-1(
-1$
-#12000000
-0!
-1#
-#13000000
-1!
-1%
-0'
-#14000000
-0!
-0#
-#15000000
-1!
-0%
-1&
-0(
-0$
-#16000000
-0!
-1#
-#17000000
-1!
-1%
-0&
-1'
-#18000000
-0!
-#19000000
-1!
-1&
-0'
-1(
-1$
-#20000000
-0!
-#21000000
-1!
-1'
-0(
-0$
-#22000000
-0!
-#23000000
-1!
-1(
-1$
-#24000000
-0!
-0#
-#25000000
-1!
-0%
-#26000000
-0!
-#27000000
-1!
-0&
-#28000000
-0!
-#29000000
-1!
-0'
-#30000000
-0!
-#31000000
-1!
-0(
-0$
-#32000000
-0!
-#33000000
-1!
-#34000000
-0!
-#35000000
-1!
-#36000000
-0!
-#37000000
-1!
-#38000000
-0!
-#39000000
-1!
-#40000000
-0!
-#41000000
-1!
-#42000000
-0!
-#43000000
-1!
-#44000000
-0!
-#45000000
-1!
-#46000000
-0!
-#47000000
-1!
-#48000000
-0!
-#49000000
-1!
-#50000000
-0!
-#51000000
-1!
-#52000000
-0!
-#53000000
-1!
-#54000000
-0!
-#55000000
-1!
-#56000000
-0!
-#57000000
-1!
-#58000000
-0!
-#59000000
-1!
-#60000000
-0!
-#61000000
-1!
-#62000000
-0!
-#63000000
-1!
-#64000000
-0!
-#65000000
-1!
-#66000000

crates/fayalite/tests/ui/hdl_types.stderr

@@ -1,4 +1,4 @@
-error: top-level #[hdl] can only be used on structs, enums, type aliases, or functions
+error: top-level #[hdl] can only be used on structs, enums, or functions
  --> tests/ui/hdl_types.rs:5:1
   |
 5 | #[hdl]

crates/fayalite/visit_types.json

@@ -1047,9 +1047,9 @@
                 "clock_domain()": "Visible",
                 "init()": "Visible"
             },
-            "generics": "<T: Type, R: ResetType>",
+            "generics": "<T: Type>",
-            "fold_where": "T: Fold<State>, R: Fold<State>",
+            "fold_where": "T: Fold<State>",
-            "visit_where": "T: Visit<State>, R: Visit<State>"
+            "visit_where": "T: Visit<State>"
         },
         "Wire": {
             "data": {
@@ -1078,8 +1078,6 @@
                 "$kind": "Enum",
                 "Wire": "Visible",
                 "Reg": "Visible",
-                "RegSync": "Visible",
-                "RegAsync": "Visible",
                 "Instance": "Visible"
             }
         },
@@ -1138,10 +1136,7 @@
                 "$kind": "Struct",
                 "annotations": "Visible",
                 "reg": "Visible"
-            },
+            }
-            "generics": "<R: ResetType>",
-            "fold_where": "R: Fold<State>",
-            "visit_where": "R: Visit<State>"
         },
         "StmtWire": {
             "data": {
@@ -1224,8 +1219,6 @@
                 "ModuleIO": "Visible",
                 "MemPort": "Visible",
                 "Reg": "Visible",
-                "RegSync": "Visible",
-                "RegAsync": "Visible",
                 "Wire": "Visible",
                 "Instance": "Visible"
             }

scripts/check-copyright.sh

@@ -46,7 +46,7 @@ function main()
         */LICENSE.md|*/Notices.txt)
             # copyright file
             ;;
-        /crates/fayalite/tests/ui/*.stderr|/crates/fayalite/tests/sim/expected/*.vcd|/crates/fayalite/tests/sim/expected/*.txt)
+        /crates/fayalite/tests/ui/*.stderr)
             # file that can't contain copyright header
             ;;
         /.forgejo/workflows/*.yml|*/.gitignore|*.toml)