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Author SHA1 Message Date
11ddbc43c7
writing VCD for combinatorial circuits works!
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2024-11-20 22:53:54 -08:00
c4b5d00419
WIP adding VCD output 2024-11-20 22:53:54 -08:00
09aa9fbc78
wire up simulator trace writing interface 2024-11-20 22:53:54 -08:00
288a6b71b9
WIP adding VCD output 2024-11-20 22:53:54 -08:00
0095570f19
simple combinatorial simulation works! 2024-11-20 22:53:54 -08:00
f54e55a143
Simulation::settle_step() works for simple modules 2024-11-20 22:53:54 -08:00
a6e40839ac
simulator WIP: use petgraph for topological sort over assignments 2024-11-20 22:53:54 -08:00
3106a6fff6
working on simulator... 2024-11-20 22:53:54 -08:00
f338f37d3e
working on simulator 2024-11-20 22:53:54 -08:00
277d3e0d4d
working on simulator 2024-11-20 22:53:54 -08:00
b288d6f8f2
add missing copyright headers 2024-11-20 22:53:54 -08:00
479d59b287
WIP implementing simulator 2024-11-20 22:53:54 -08:00
6f904148c4
WIP adding simulator 2024-11-20 22:53:54 -08:00
3ea0d98924
always write formal cache json
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2024-11-20 22:51:40 -08:00

View file

@ -653,7 +653,6 @@ impl FormalArgs {
self.sby.display() self.sby.display()
))) )))
}; };
if do_cache {
fs::write( fs::write(
cache_file, cache_file,
serde_json::to_string_pretty(&FormalCache { serde_json::to_string_pretty(&FormalCache {
@ -667,7 +666,6 @@ impl FormalArgs {
}) })
.expect("serialization shouldn't ever fail"), .expect("serialization shouldn't ever fail"),
)?; )?;
}
result result
} }
} }