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Author SHA1 Message Date
e2653a3245
writing VCD for combinatorial circuits works!
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2024-11-20 22:36:26 -08:00
f8b0ab45b0
WIP adding VCD output 2024-11-20 22:14:44 -08:00
01dafcea0f
wire up simulator trace writing interface 2024-11-20 22:14:44 -08:00
18ddab26ba
WIP adding VCD output 2024-11-20 22:14:44 -08:00
2842c2839f
simple combinatorial simulation works! 2024-11-20 22:14:44 -08:00
41139d09dc
Simulation::settle_step() works for simple modules 2024-11-20 22:14:44 -08:00
2edd9defd1
simulator WIP: use petgraph for topological sort over assignments 2024-11-20 22:14:44 -08:00
1cb394674a
working on simulator... 2024-11-20 22:14:44 -08:00
435514654c
working on simulator 2024-11-20 22:14:44 -08:00
86c711c36e
working on simulator 2024-11-20 22:14:44 -08:00
1a769b8162
add missing copyright headers 2024-11-20 22:14:44 -08:00
dfca5e7c8f
WIP implementing simulator 2024-11-20 22:14:44 -08:00
747ad535a2
WIP adding simulator 2024-11-20 22:14:44 -08:00

View file

@ -653,19 +653,21 @@ impl FormalArgs {
self.sby.display() self.sby.display()
))) )))
}; };
fs::write( if do_cache {
cache_file, fs::write(
serde_json::to_string_pretty(&FormalCache { cache_file,
version: FormalCacheVersion::CURRENT, serde_json::to_string_pretty(&FormalCache {
contents_hash: contents_hash.unwrap(), version: FormalCacheVersion::CURRENT,
stdout_stderr: captured_output, contents_hash: contents_hash.unwrap(),
result: match &result { stdout_stderr: captured_output,
Ok(FormalOutput { verilog: _ }) => Ok(FormalCacheOutput {}), result: match &result {
Err(error) => Err(error.to_string()), Ok(FormalOutput { verilog: _ }) => Ok(FormalCacheOutput {}),
}, Err(error) => Err(error.to_string()),
}) },
.expect("serialization shouldn't ever fail"), })
)?; .expect("serialization shouldn't ever fail"),
)?;
}
result result
} }
} }