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change register names to end in _reg by convention

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This commit is contained in:
Jacob Lifshay 2024-10-06 18:50:09 -07:00
parent ec77559e2b
commit e05c368688
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
4 changed files with 87 additions and 69 deletions
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8
crates/fayalite/examples/blinky.rs
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@ -17,15 +17,15 @@ fn blinky(clock_frequency: u64) {
let max_value = clock_frequency / 2 - 1;
let int_ty = UInt::range_inclusive(0..=max_value);
#[hdl]
let counter: UInt = reg_builder().clock_domain(cd).reset(0u8.cast_to(int_ty));
let counter_reg: UInt = reg_builder().clock_domain(cd).reset(0u8.cast_to(int_ty));
#[hdl]
let output_reg: Bool = reg_builder().clock_domain(cd).reset(false);
#[hdl]
if counter.cmp_eq(max_value) {
connect_any(counter, 0u8);
if counter_reg.cmp_eq(max_value) {
connect_any(counter_reg, 0u8);
connect(output_reg, !output_reg);
} else {
connect_any(counter, counter + 1_hdl_u1);
connect_any(counter_reg, counter_reg + 1_hdl_u1);
}
#[hdl]
let led: Bool = m.output();