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add simulator support for sim-only values
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This commit is contained in:
Jacob Lifshay 2025-09-01 04:46:24 -07:00
parent d3dd66cbf0
commit db9b1c202c
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
52 changed files with 5441 additions and 819 deletions
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98
crates/fayalite/tests/sim.rs
View file

@ -9,7 +9,7 @@ use fayalite::{
sim::vcd::VcdWriterDecls,
util::RcWriter,
};
use std::num::NonZeroUsize;
use std::{collections::BTreeMap, num::NonZeroUsize, rc::Rc};
#[hdl_module(outline_generated)]
pub fn connect_const() {
@ -1626,3 +1626,99 @@ fn test_ripple_counter() {
panic!();
}
}
/// use `Rc` to ensure you can use `!Send + !Sync` types
type SimOnlyTestMap = BTreeMap<String, Rc<str>>;
#[hdl_module(outline_generated, extern)]
fn sim_only_connects_helper() {
#[hdl]
let cd: ClockDomain = m.input();
#[hdl]
let inp: SimOnly<SimOnlyTestMap> = m.input();
#[hdl]
let out: SimOnly<SimOnlyTestMap> = m.output();
m.extern_module_simulation_fn((cd, inp, out), |(cd, inp, out), mut sim| async move {
sim.write(out, SimOnlyValue::default()).await;
loop {
sim.wait_for_clock_edge(cd.clk).await;
let mut map = sim.read(inp).await;
let foo = map.get("foo").cloned().unwrap_or_default();
map.insert(String::from("bar"), foo);
map.insert(String::from("foo"), Rc::from("baz"));
sim.write(out, map).await;
}
});
}
#[hdl_module(outline_generated)]
pub fn sim_only_connects() {
#[hdl]
let cd: ClockDomain = m.input();
#[hdl]
let inp: SimOnly<SimOnlyTestMap> = m.input();
#[hdl]
let out1: SimOnly<SimOnlyTestMap> = m.output();
#[hdl]
let out2: SimOnly<SimOnlyTestMap> = m.output();
#[hdl]
let out3: SimOnly<SimOnlyTestMap> = m.output();
#[hdl]
let helper1 = instance(sim_only_connects_helper());
#[hdl]
let delay1: SimOnly<SimOnlyTestMap> = reg_builder()
.clock_domain(cd)
.reset(SimOnly::<SimOnlyTestMap>::new().uninit());
#[hdl]
let delay1_empty: Bool = reg_builder().clock_domain(cd).reset(true);
connect(helper1.cd, cd);
connect(helper1.inp, delay1);
connect(out1, delay1);
#[hdl]
if delay1_empty {
connect(helper1.inp, inp);
connect(out1, inp);
}
connect(delay1, inp);
connect(delay1_empty, false);
connect(out2, helper1.out);
#[hdl]
let helper2 = instance(sim_only_connects_helper());
connect(helper2.cd, cd);
connect(helper2.inp, out2);
connect(out3, helper2.out);
}
#[test]
fn test_sim_only_connects() {
let _n = SourceLocation::normalize_files_for_tests();
let mut sim = Simulation::new(sim_only_connects());
let mut writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
sim.write(sim.io().cd.rst, true);
sim.write(
sim.io().inp,
SimOnlyValue::new(BTreeMap::from_iter([(
String::from("extra"),
Rc::from("value"),
)])),
);
for _ in 0..8 {
sim.write(sim.io().cd.clk, false);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().cd.clk, true);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().cd.rst, false);
}
sim.flush_traces().unwrap();
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
if vcd != include_str!("sim/expected/sim_only_connects.vcd") {
panic!();
}
let sim_debug = format!("{sim:#?}");
println!("#######\n{sim_debug}\n#######");
if sim_debug != include_str!("sim/expected/sim_only_connects.txt") {
panic!();
}
}

9
crates/fayalite/tests/sim/expected/array_rw.txt
View file

@ -239,6 +239,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -480,6 +486,9 @@ Simulation {
255,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::array_rw,

9
crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
View file

@ -30,6 +30,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -84,6 +90,9 @@ Simulation {
0,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::conditional_assignment_last,

9
crates/fayalite/tests/sim/expected/connect_const.txt
View file

@ -22,6 +22,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -60,6 +66,9 @@ Simulation {
5,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::connect_const,

9
crates/fayalite/tests/sim/expected/connect_const_reset.txt
View file

@ -34,6 +34,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -89,6 +95,9 @@ Simulation {
1,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::connect_const_reset,

9
crates/fayalite/tests/sim/expected/counter_async.txt
View file

@ -71,6 +71,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -195,6 +201,9 @@ Simulation {
4,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::counter,

9
crates/fayalite/tests/sim/expected/counter_sync.txt
View file

@ -67,6 +67,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -176,6 +182,9 @@ Simulation {
4,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::counter,

9
crates/fayalite/tests/sim/expected/duplicate_names.txt
View file

@ -30,6 +30,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -80,6 +86,9 @@ Simulation {
6,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::duplicate_names,

9
crates/fayalite/tests/sim/expected/enums.txt
View file

@ -529,6 +529,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -1304,6 +1310,9 @@ Simulation {
15,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::enums,

33
crates/fayalite/tests/sim/expected/extern_module.txt
View file

@ -22,6 +22,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -50,6 +56,9 @@ Simulation {
1,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::extern_module,
@ -146,6 +155,30 @@ Simulation {
),
f: ...,
},
sim_io_to_generator_map: {
ModuleIO {
name: extern_module::i,
is_input: true,
ty: Bool,
..
}: ModuleIO {
name: extern_module::i,
is_input: true,
ty: Bool,
..
},
ModuleIO {
name: extern_module::o,
is_input: false,
ty: Bool,
..
}: ModuleIO {
name: extern_module::o,
is_input: false,
ty: Bool,
..
},
},
source_location: SourceLocation(
module-XXXXXXXXXX.rs:4:1,
),

52
crates/fayalite/tests/sim/expected/extern_module2.txt
View file

@ -26,6 +26,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -55,6 +61,9 @@ Simulation {
101,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::extern_module2,
@ -183,6 +192,41 @@ Simulation {
),
f: ...,
},
sim_io_to_generator_map: {
ModuleIO {
name: extern_module2::clk,
is_input: true,
ty: Clock,
..
}: ModuleIO {
name: extern_module2::clk,
is_input: true,
ty: Clock,
..
},
ModuleIO {
name: extern_module2::en,
is_input: true,
ty: Bool,
..
}: ModuleIO {
name: extern_module2::en,
is_input: true,
ty: Bool,
..
},
ModuleIO {
name: extern_module2::o,
is_input: false,
ty: UInt<8>,
..
}: ModuleIO {
name: extern_module2::o,
is_input: false,
ty: UInt<8>,
..
},
},
source_location: SourceLocation(
module-XXXXXXXXXX.rs:5:1,
),
@ -211,12 +255,19 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
},
write: None,
},
@ -224,6 +275,7 @@ Simulation {
ty: Clock,
value: OpaqueSimValue {
bits: 0x1_u1,
sim_only_values: [],
},
},
},

9
crates/fayalite/tests/sim/expected/memories.txt
View file

@ -175,6 +175,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 1,
@ -562,6 +568,9 @@ Simulation {
1,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::memories,

9
crates/fayalite/tests/sim/expected/memories2.txt
View file

@ -224,6 +224,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 1,
@ -590,6 +596,9 @@ Simulation {
1,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::memories2,

9
crates/fayalite/tests/sim/expected/memories3.txt
View file

@ -503,6 +503,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 1,
@ -1478,6 +1484,9 @@ Simulation {
0,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::memories3,

9
crates/fayalite/tests/sim/expected/mod1.txt
View file

@ -82,6 +82,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -208,6 +214,9 @@ Simulation {
15,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::mod1,

105
crates/fayalite/tests/sim/expected/ripple_counter.txt
View file

@ -283,6 +283,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -691,6 +697,9 @@ Simulation {
0,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::ripple_counter,
@ -787,6 +796,30 @@ Simulation {
),
f: ...,
},
sim_io_to_generator_map: {
ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
}: ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
},
ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
}: ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
},
},
source_location: SourceLocation(
module-XXXXXXXXXX-2.rs:4:1,
),
@ -815,12 +848,19 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 3, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 33, len: 1 },
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
},
write: None,
},
@ -828,6 +868,7 @@ Simulation {
ty: Clock,
value: OpaqueSimValue {
bits: 0x0_u1,
sim_only_values: [],
},
},
},
@ -884,6 +925,30 @@ Simulation {
),
f: ...,
},
sim_io_to_generator_map: {
ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
}: ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
},
ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
}: ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
},
},
source_location: SourceLocation(
module-XXXXXXXXXX-2.rs:4:1,
),
@ -912,12 +977,19 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 6, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 44, len: 1 },
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
},
write: None,
},
@ -925,6 +997,7 @@ Simulation {
ty: Clock,
value: OpaqueSimValue {
bits: 0x0_u1,
sim_only_values: [],
},
},
},
@ -981,6 +1054,30 @@ Simulation {
),
f: ...,
},
sim_io_to_generator_map: {
ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
}: ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
},
ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
}: ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
},
},
source_location: SourceLocation(
module-XXXXXXXXXX-2.rs:4:1,
),
@ -1009,12 +1106,19 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 9, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 55, len: 1 },
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
},
write: None,
},
@ -1022,6 +1126,7 @@ Simulation {
ty: Clock,
value: OpaqueSimValue {
bits: 0x0_u1,
sim_only_values: [],
},
},
},

9
crates/fayalite/tests/sim/expected/shift_register.txt
View file

@ -83,6 +83,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -257,6 +263,9 @@ Simulation {
0,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::shift_register,

1636
crates/fayalite/tests/sim/expected/sim_only_connects.txt Normal file
View file

File diff suppressed because it is too large Load diff

185
crates/fayalite/tests/sim/expected/sim_only_connects.vcd Normal file
View file

@ -0,0 +1,185 @@
$timescale 1 ps $end
$scope module sim_only_connects $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$upscope $end
$var string 1 # inp $end
$var string 1 $ out1 $end
$var string 1 % out2 $end
$var string 1 & out3 $end
$scope struct helper1 $end
$scope struct cd $end
$var wire 1 + clk $end
$var wire 1 , rst $end
$upscope $end
$var string 1 - inp $end
$var string 1 . out $end
$upscope $end
$scope module sim_only_connects_helper $end
$scope struct cd $end
$var wire 1 ' clk $end
$var wire 1 ( rst $end
$upscope $end
$var string 1 ) inp $end
$var string 1 * out $end
$upscope $end
$var string 1 / delay1 $end
$var reg 1 0 delay1_empty $end
$scope struct helper2 $end
$scope struct cd $end
$var wire 1 5 clk $end
$var wire 1 6 rst $end
$upscope $end
$var string 1 7 inp $end
$var string 1 8 out $end
$upscope $end
$scope module sim_only_connects_helper_2 $end
$scope struct cd $end
$var wire 1 1 clk $end
$var wire 1 2 rst $end
$upscope $end
$var string 1 3 inp $end
$var string 1 4 out $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
1"
s{\"extra\":\x20\"value\"} #
s{} $
s{} %
s{} &
0'
1(
s{} )
s{} *
0+
1,
s{} -
s{} .
s{} /
00
01
12
s{} 3
s{} 4
05
16
s{} 7
s{} 8
$end
#1000000
1!
1'
1+
10
11
15
s{\"extra\":\x20\"value\"} $
s{\"extra\":\x20\"value\"} )
s{\"extra\":\x20\"value\"} -
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} *
s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 4
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} %
s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} &
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} .
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 3
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 7
s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 8
#2000000
0!
0"
0'
0(
0+
0,
01
02
05
06
#3000000
1!
1'
1+
s{\"extra\":\x20\"value\"} /
00
11
15
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} &
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8
#4000000
0!
0'
0+
01
05
#5000000
1!
1'
1+
11
15
#6000000
0!
0'
0+
01
05
#7000000
1!
1'
1+
11
15
#8000000
0!
0'
0+
01
05
#9000000
1!
1'
1+
11
15
#10000000
0!
0'
0+
01
05
#11000000
1!
1'
1+
11
15
#12000000
0!
0'
0+
01
05
#13000000
1!
1'
1+
11
15
#14000000
0!
0'
0+
01
05
#15000000
1!
1'
1+
11
15
#16000000

183
crates/fayalite/tests/ui/simvalue_is_not_internable.stderr
View file

@ -45,6 +45,64 @@ note: required by a bound in `fayalite::intern::Interned`
| pub struct Interned<T: ?Sized + 'static + Send + Sync> {
| ^^^^ required by this bound in `Interned`
error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
--> tests/ui/simvalue_is_not_internable.rs:11:26
|
11 | fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
| ^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
|
= help: within `SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>`
note: required because it appears within the type `DynSimOnlyValue`
--> src/sim/value/sim_only_value_unsafe.rs
|
| pub struct DynSimOnlyValue(Rc<dyn DynSimOnlyValueTrait>);
| ^^^^^^^^^^^^^^^
note: required because it appears within the type `PhantomData<DynSimOnlyValue>`
--> $RUST/core/src/marker.rs
|
| pub struct PhantomData<T: PointeeSized>;
| ^^^^^^^^^^^
note: required because it appears within the type `alloc::raw_vec::RawVec<DynSimOnlyValue>`
--> $RUST/alloc/src/raw_vec/mod.rs
|
| pub(crate) struct RawVec<T, A: Allocator = Global> {
| ^^^^^^
note: required because it appears within the type `Vec<DynSimOnlyValue>`
--> $RUST/alloc/src/vec/mod.rs
|
| pub struct Vec<T, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global> {
| ^^^
note: required because it appears within the type `OpaqueSimValue`
--> src/ty.rs
|
| pub struct OpaqueSimValue {
| ^^^^^^^^^^^^^^
note: required because it appears within the type `value::SimValueInner<()>`
--> src/sim/value.rs
|
| struct SimValueInner<T: Type> {
| ^^^^^^^^^^^^^
note: required because it appears within the type `UnsafeCell<value::SimValueInner<()>>`
--> $RUST/core/src/cell.rs
|
| pub struct UnsafeCell<T: ?Sized> {
| ^^^^^^^^^^
note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
--> src/util/alternating_cell.rs
|
| pub(crate) struct AlternatingCell<T: ?Sized> {
| ^^^^^^^^^^^^^^^
note: required because it appears within the type `SimValue<()>`
--> src/sim/value.rs
|
| pub struct SimValue<T: Type> {
| ^^^^^^^^
note: required by a bound in `fayalite::intern::Interned`
--> src/intern.rs
|
| pub struct Interned<T: ?Sized + 'static + Send + Sync> {
| ^^^^ required by this bound in `Interned`
error[E0277]: the trait bound `SimValue<()>: Intern` is not satisfied
--> tests/ui/simvalue_is_not_internable.rs:12:26
|
@ -138,6 +196,73 @@ help: consider dereferencing here
12 | Intern::intern_sized(*v)
| +
error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
--> tests/ui/simvalue_is_not_internable.rs:12:26
|
12 | Intern::intern_sized(v)
| -------------------- ^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
| |
| required by a bound introduced by this call
|
= help: within `SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>`
note: required because it appears within the type `DynSimOnlyValue`
--> src/sim/value/sim_only_value_unsafe.rs
|
| pub struct DynSimOnlyValue(Rc<dyn DynSimOnlyValueTrait>);
| ^^^^^^^^^^^^^^^
note: required because it appears within the type `PhantomData<DynSimOnlyValue>`
--> $RUST/core/src/marker.rs
|
| pub struct PhantomData<T: PointeeSized>;
| ^^^^^^^^^^^
note: required because it appears within the type `alloc::raw_vec::RawVec<DynSimOnlyValue>`
--> $RUST/alloc/src/raw_vec/mod.rs
|
| pub(crate) struct RawVec<T, A: Allocator = Global> {
| ^^^^^^
note: required because it appears within the type `Vec<DynSimOnlyValue>`
--> $RUST/alloc/src/vec/mod.rs
|
| pub struct Vec<T, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global> {
| ^^^
note: required because it appears within the type `OpaqueSimValue`
--> src/ty.rs
|
| pub struct OpaqueSimValue {
| ^^^^^^^^^^^^^^
note: required because it appears within the type `value::SimValueInner<()>`
--> src/sim/value.rs
|
| struct SimValueInner<T: Type> {
| ^^^^^^^^^^^^^
note: required because it appears within the type `UnsafeCell<value::SimValueInner<()>>`
--> $RUST/core/src/cell.rs
|
| pub struct UnsafeCell<T: ?Sized> {
| ^^^^^^^^^^
note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
--> src/util/alternating_cell.rs
|
| pub(crate) struct AlternatingCell<T: ?Sized> {
| ^^^^^^^^^^^^^^^
note: required because it appears within the type `SimValue<()>`
--> src/sim/value.rs
|
| pub struct SimValue<T: Type> {
| ^^^^^^^^
note: required by a bound in `intern_sized`
--> src/intern.rs
|
| pub trait Intern: Any + Send + Sync {
| ^^^^ required by this bound in `Intern::intern_sized`
| fn intern(&self) -> Interned<Self>;
| fn intern_sized(self) -> Interned<Self>
| ------------ required by a bound in this associated function
help: consider dereferencing here
|
12 | Intern::intern_sized(*v)
| +
error[E0277]: `Cell<util::alternating_cell::State>` cannot be shared between threads safely
--> tests/ui/simvalue_is_not_internable.rs:12:5
|
@ -184,3 +309,61 @@ note: required by a bound in `fayalite::intern::Interned`
|
| pub struct Interned<T: ?Sized + 'static + Send + Sync> {
| ^^^^ required by this bound in `Interned`
error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
--> tests/ui/simvalue_is_not_internable.rs:12:5
|
12 | Intern::intern_sized(v)
| ^^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
|
= help: within `SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>`
note: required because it appears within the type `DynSimOnlyValue`
--> src/sim/value/sim_only_value_unsafe.rs
|
| pub struct DynSimOnlyValue(Rc<dyn DynSimOnlyValueTrait>);
| ^^^^^^^^^^^^^^^
note: required because it appears within the type `PhantomData<DynSimOnlyValue>`
--> $RUST/core/src/marker.rs
|
| pub struct PhantomData<T: PointeeSized>;
| ^^^^^^^^^^^
note: required because it appears within the type `alloc::raw_vec::RawVec<DynSimOnlyValue>`
--> $RUST/alloc/src/raw_vec/mod.rs
|
| pub(crate) struct RawVec<T, A: Allocator = Global> {
| ^^^^^^
note: required because it appears within the type `Vec<DynSimOnlyValue>`
--> $RUST/alloc/src/vec/mod.rs
|
| pub struct Vec<T, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global> {
| ^^^
note: required because it appears within the type `OpaqueSimValue`
--> src/ty.rs
|
| pub struct OpaqueSimValue {
| ^^^^^^^^^^^^^^
note: required because it appears within the type `value::SimValueInner<()>`
--> src/sim/value.rs
|
| struct SimValueInner<T: Type> {
| ^^^^^^^^^^^^^
note: required because it appears within the type `UnsafeCell<value::SimValueInner<()>>`
--> $RUST/core/src/cell.rs
|
| pub struct UnsafeCell<T: ?Sized> {
| ^^^^^^^^^^
note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
--> src/util/alternating_cell.rs
|
| pub(crate) struct AlternatingCell<T: ?Sized> {
| ^^^^^^^^^^^^^^^
note: required because it appears within the type `SimValue<()>`
--> src/sim/value.rs
|
| pub struct SimValue<T: Type> {
| ^^^^^^^^
note: required by a bound in `fayalite::intern::Interned`
--> src/intern.rs
|
| pub struct Interned<T: ?Sized + 'static + Send + Sync> {
| ^^^^ required by this bound in `Interned`