fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s
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3 changed files with 37 additions and 22 deletions
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@ -22,7 +22,8 @@ macro_rules! __cfg_expansion_helper {
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$cfg:ident($($expr:tt)*),
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$($unevaluated_cfgs:ident($($unevaluated_exprs:tt)*),)*
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]
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#[$after_evaluation:path:($($after_evaluation_attr_args:tt)*)] {$($after_evaluation_args:tt)*}
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// pass as tt so we get right span for attribute
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$after_evaluation_attr:tt $after_evaluation_body:tt
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) => {
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#[$cfg($($expr)*)]
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$crate::__cfg_expansion_helper! {
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@ -33,7 +34,7 @@ macro_rules! __cfg_expansion_helper {
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[
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$($unevaluated_cfgs($($unevaluated_exprs)*),)*
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]
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#[$after_evaluation:($($after_evaluation_attr_args)*)] {$($after_evaluation_args)*}
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$after_evaluation_attr $after_evaluation_body
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}
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#[$cfg(not($($expr)*))]
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$crate::__cfg_expansion_helper! {
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@ -44,7 +45,7 @@ macro_rules! __cfg_expansion_helper {
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[
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$($unevaluated_cfgs($($unevaluated_exprs)*),)*
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]
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#[$after_evaluation:($($after_evaluation_attr_args)*)] {$($after_evaluation_args)*}
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$after_evaluation_attr $after_evaluation_body
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}
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};
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(
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@ -52,12 +53,14 @@ macro_rules! __cfg_expansion_helper {
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$($evaluated_cfgs:ident($($evaluated_exprs:tt)*) = $evaluated_results:ident,)*
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]
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[]
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#[$after_evaluation:path:($($after_evaluation_attr_args:tt)*)] {$($after_evaluation_args:tt)*}
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// don't use #[...] so we get right span for `#` and `[]` of attribute
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{$($after_evaluation_attr:tt)*} {$($after_evaluation_body:tt)*}
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) => {
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#[$after_evaluation([
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$($after_evaluation_attr)*
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#[__evaluated_cfgs([
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$($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
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] $($after_evaluation_attr_args)*)]
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$($after_evaluation_args)*
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])]
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$($after_evaluation_body)*
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};
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}
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@ -4288,7 +4288,8 @@ circuit check_deduce_resets:
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};
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}
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#[hdl_module(outline_generated)]
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// intentionally not outline_generated to ensure we get correct macro hygiene
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#[hdl_module]
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pub fn check_cfgs<#[cfg(cfg_false_for_tests)] A: Type, #[cfg(cfg_true_for_tests)] B: Type>(
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#[cfg(cfg_false_for_tests)] a: A,
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#[cfg(cfg_true_for_tests)] b: B,
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@ -4335,12 +4336,12 @@ fn test_cfgs() {
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"/test/check_cfgs.fir": r"FIRRTL version 3.2.0
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circuit check_cfgs:
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type Ty0 = {b: UInt<8>}
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module check_cfgs: @[module-XXXXXXXXXX.rs 1:1]
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input i_b: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
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output o_b: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
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wire w: Ty0 @[module-XXXXXXXXXX.rs 3:1]
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connect o_b, w.b @[module-XXXXXXXXXX.rs 5:1]
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connect w.b, i_b @[module-XXXXXXXXXX.rs 6:1]
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module check_cfgs: @[the_test_file.rs 9962:1]
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input i_b: UInt<8> @[the_test_file.rs 9979:20]
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output o_b: UInt<8> @[the_test_file.rs 9992:24]
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wire w: Ty0 @[the_test_file.rs 9981:25]
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connect o_b, w.b @[the_test_file.rs 9993:9]
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connect w.b, i_b @[the_test_file.rs 9994:9]
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",
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};
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}
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