add test for cfgs

crates/fayalite/build.rs

@@ -5,6 +5,9 @@ use std::{env, fs, path::Path};
 
 fn main() {
     println!("cargo::rustc-check-cfg=cfg(todo)");
+    println!("cargo::rustc-check-cfg=cfg(cfg_false_for_tests)");
+    println!("cargo::rustc-check-cfg=cfg(cfg_true_for_tests)");
+    println!("cargo::rustc-cfg=cfg_true_for_tests");
     let path = "visit_types.json";
     println!("cargo::rerun-if-changed={path}");
     println!("cargo::rerun-if-changed=build.rs");

crates/fayalite/tests/module.rs

@@ -4287,3 +4287,60 @@ circuit check_deduce_resets:
 ",
     };
 }
+
+#[hdl_module(outline_generated)]
+pub fn check_cfgs<#[cfg(cfg_false_for_tests)] A: Type, #[cfg(cfg_true_for_tests)] B: Type>(
+    #[cfg(cfg_false_for_tests)] a: A,
+    #[cfg(cfg_true_for_tests)] b: B,
+) {
+    #[hdl]
+    struct S<#[cfg(cfg_false_for_tests)] A, #[cfg(cfg_true_for_tests)] B> {
+        #[cfg(cfg_false_for_tests)]
+        a: A,
+        #[cfg(cfg_true_for_tests)]
+        b: B,
+    }
+    #[hdl]
+    #[cfg(cfg_false_for_tests)]
+    let i_a: A = m.input(a);
+    #[hdl]
+    #[cfg(cfg_true_for_tests)]
+    let i_b: B = m.input(b);
+    #[hdl]
+    let w: S<UInt<8>> = wire();
+    #[cfg(cfg_false_for_tests)]
+    {
+        #[hdl]
+        let o_a: A = m.output(a);
+        connect(o_a, w.a.cast_bits_to(a));
+        connect_any(w.a, i_a.cast_to_bits());
+    }
+    #[cfg(cfg_true_for_tests)]
+    {
+        #[hdl]
+        let o_b: B = m.output(b);
+        connect(o_b, w.b.cast_bits_to(b));
+        connect_any(w.b, i_b.cast_to_bits());
+    }
+}
+
+#[test]
+fn test_cfgs() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_cfgs(UInt[8]);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_cfgs.fir": r"FIRRTL version 3.2.0
+circuit check_cfgs:
+    type Ty0 = {b: UInt<8>}
+    module check_cfgs: @[module-XXXXXXXXXX.rs 1:1]
+        input i_b: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
+        output o_b: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        wire w: Ty0 @[module-XXXXXXXXXX.rs 3:1]
+        connect o_b, w.b @[module-XXXXXXXXXX.rs 5:1]
+        connect w.b, i_b @[module-XXXXXXXXXX.rs 6:1]
+",
+    };
+}