simplify setting an extern module simulation

crates/fayalite/tests/sim.rs

@@ -5,14 +5,11 @@ use fayalite::{
     int::UIntValue,
     prelude::*,
     reset::ResetType,
-    sim::{
-        time::SimDuration, vcd::VcdWriterDecls, ExternModuleSimGenerator,
-        ExternModuleSimulationState, Simulation, ToSimValue,
-    },
+    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
     ty::StaticType,
     util::RcWriter,
 };
-use std::{future::IntoFuture, num::NonZeroUsize};
+use std::num::NonZeroUsize;
 
 #[hdl_module(outline_generated)]
 pub fn connect_const() {
@@ -1453,33 +1450,17 @@ pub fn extern_module() {
     let i: Bool = m.input();
     #[hdl]
     let o: Bool = m.output();
-    #[derive(Clone, Eq, PartialEq, Hash, Debug)]
-    struct Sim {
-        i: Expr<Bool>,
-        o: Expr<Bool>,
-    }
-    impl ExternModuleSimGenerator for Sim {
-        type IOType = extern_module;
-
-        fn run<'a>(
-            &'a self,
-            mut sim: ExternModuleSimulationState<Self::IOType>,
-        ) -> impl IntoFuture<Output = ()> + 'a {
-            let Self { i, o } = *self;
-            async move {
-                sim.write(o, true).await;
-                sim.advance_time(SimDuration::from_nanos(500)).await;
-                let mut invert = false;
-                loop {
-                    sim.advance_time(SimDuration::from_micros(1)).await;
-                    let v = sim.read_bool(i).await;
-                    sim.write(o, v ^ invert).await;
-                    invert = !invert;
-                }
-            }
+    m.extern_module_simulation_fn((i, o), |(i, o), mut sim| async move {
+        sim.write(o, true).await;
+        sim.advance_time(SimDuration::from_nanos(500)).await;
+        let mut invert = false;
+        loop {
+            sim.advance_time(SimDuration::from_micros(1)).await;
+            let v = sim.read_bool(i).await;
+            sim.write(o, v ^ invert).await;
+            invert = !invert;
         }
-    }
-    m.extern_module_simulation(Sim { i, o });
+    });
 }
 
 #[test]

crates/fayalite/tests/sim/expected/extern_module.txt

@@ -128,31 +128,27 @@ Simulation {
                 },
                 did_initial_settle: true,
             },
-            io_ty: Bundle {
-                #[hdl(flip)] /* offset = 0 */
-                i: Bool,
-                /* offset = 1 */
-                o: Bool,
-            },
             sim: ExternModuleSimulation {
-                generator: Sim {
-                    i: ModuleIO {
-                        name: extern_module::i,
-                        is_input: true,
-                        ty: Bool,
-                        ..
-                    },
-                    o: ModuleIO {
-                        name: extern_module::o,
-                        is_input: false,
-                        ty: Bool,
-                        ..
-                    },
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: extern_module::i,
+                            is_input: true,
+                            ty: Bool,
+                            ..
+                        },
+                        ModuleIO {
+                            name: extern_module::o,
+                            is_input: false,
+                            ty: Bool,
+                            ..
+                        },
+                    ),
+                    f: ...,
                 },
                 source_location: SourceLocation(
                     module-XXXXXXXXXX.rs:4:1,
                 ),
-                _phantom: PhantomData<fayalite::bundle::Bundle>,
             },
             running_generator: Some(
                 ...,