libre-chip/fayalite
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add repeat()

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This commit is contained in:
Jacob Lifshay 2024-09-22 18:56:26 -07:00
parent 78edfc97b2
commit a701f99fd6
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
2 changed files with 17 additions and 2 deletions
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17
crates/fayalite/src/expr.rs
View file

@ -9,7 +9,7 @@ use crate::{
ops::ExprCastTo,
target::{GetTarget, Target},
},
int::{Bool, DynSize, IntType, SIntType, SIntValue, Size, UInt, UIntType, UIntValue},
int::{Bool, DynSize, IntType, SIntType, SIntValue, Size, SizeType, UInt, UIntType, UIntValue},
intern::{Intern, Interned},
memory::{DynPortType, MemPort, PortType},
module::{
@ -720,3 +720,18 @@ impl<T: Type> MakeUninitExpr for T {
ops::Uninit::new(self).to_expr()
}
}
pub fn repeat<T: Type, L: SizeType>(
element: impl ToExpr<Type = T>,
len: L,
) -> Expr<ArrayType<T, L::Size>> {
let element = element.to_expr();
let canonical_element = Expr::canonical(element);
ops::ArrayLiteral::new(
Expr::ty(element),
std::iter::repeat(canonical_element)
.take(L::Size::as_usize(len))
.collect(),
)
.to_expr()
}

2
crates/fayalite/src/prelude.rs
View file

@ -7,7 +7,7 @@ pub use crate::{
clock::{Clock, ClockDomain, ToClock},
enum_::{HdlNone, HdlOption, HdlSome},
expr::{
CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd, MakeUninitExpr,
repeat, CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd, MakeUninitExpr,
ReduceBits, ToExpr,
},
hdl, hdl_module,