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rename ClockDomain fields to clk and rst for consistency

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This commit is contained in:
Jacob Lifshay 2024-07-16 19:46:08 -07:00
parent 63fd038729
commit 86827def91
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
3 changed files with 13 additions and 13 deletions
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4
crates/fayalite/src/clock.rs
View file

@ -105,8 +105,8 @@ impl CanonicalValue for Clock {
#[derive(Copy, Clone, Debug, Eq, PartialEq, Hash, Value)]
#[hdl(fixed_type, outline_generated)]
pub struct ClockDomain {
pub clock: Clock,
pub reset: Reset,
pub clk: Clock,
pub rst: Reset,
}
pub trait ToClock {

10
crates/fayalite/src/firrtl.rs
View file

@ -2013,21 +2013,21 @@ impl<'a> Exporter<'a> {
self.targeted_annotations(module_name, vec![], &annotations);
let name = self.module.ns.get(reg.name_id());
let ty = self.type_state.ty(reg.ty());
let clock = self.expr(reg.clock_domain().clock.to_dyn(), &definitions, false);
let clk = self.expr(reg.clock_domain().clk.to_dyn(), &definitions, false);
if let Some(init) = reg.init() {
let reset =
self.expr(reg.clock_domain().reset.to_dyn(), &definitions, false);
let rst =
self.expr(reg.clock_domain().rst.to_dyn(), &definitions, false);
let init = self.expr(init.to_dyn(), &definitions, false);
writeln!(
body,
"{indent}regreset {name}: {ty}, {clock}, {reset}, {init}{}",
"{indent}regreset {name}: {ty}, {clk}, {rst}, {init}{}",
FileInfo::new(reg.source_location()),
)
.unwrap();
} else {
writeln!(
body,
"{indent}reg {name}: {ty}, {clock}{}",
"{indent}reg {name}: {ty}, {clk}{}",
FileInfo::new(reg.source_location()),
)
.unwrap();

12
crates/fayalite/tests/module.rs
View file

@ -31,8 +31,8 @@ pub fn my_module(width: usize) {
let rst: SyncReset = m.input();
#[hdl]
let clock_domain: ClockDomain = m.wire();
m.connect(clock_domain.clock, clk);
m.connect(clock_domain.reset, rst.to_reset());
m.connect(clock_domain.clk, clk);
m.connect(clock_domain.rst, rst.to_reset());
#[hdl]
let i: UInt<8> = m.input();
#[hdl]
@ -94,7 +94,7 @@ fn test_mymodule() {
circuit my_module:
type Ty0 = {`0`: UInt<32>, `1`: SInt<5>}
type Ty1 = {|A, B: UInt<8>, C: UInt<1>[3]|}
type Ty2 = {clock: Clock, `reset`: Reset}
type Ty2 = {clk: Clock, rst: Reset}
type Ty3 = {flip i: UInt<8>, o: UInt<8>}
module my_module: @[module-XXXXXXXXXX.rs 1:1]
input clk: Clock @[module-XXXXXXXXXX.rs 2:1]
@ -106,14 +106,14 @@ circuit my_module:
output o3: Ty0 @[module-XXXXXXXXXX.rs 11:1]
output o4: Ty1 @[module-XXXXXXXXXX.rs 20:1]
wire clock_domain: Ty2 @[module-XXXXXXXXXX.rs 4:1]
connect clock_domain.clock, clk @[module-XXXXXXXXXX.rs 5:1]
connect clock_domain.`reset`, rst @[module-XXXXXXXXXX.rs 6:1]
connect clock_domain.clk, clk @[module-XXXXXXXXXX.rs 5:1]
connect clock_domain.rst, rst @[module-XXXXXXXXXX.rs 6:1]
wire _bundle_literal_expr: Ty0
connect _bundle_literal_expr.`0`, UInt<32>(0h5)
connect _bundle_literal_expr.`1`, SInt<5>(-0h3)
connect o3, _bundle_literal_expr @[module-XXXXXXXXXX.rs 12:1]
inst m2 of module2 @[module-XXXXXXXXXX.rs 13:1]
regreset r: UInt<8>, clock_domain.clock, clock_domain.`reset`, UInt<8>(0h8) @[module-XXXXXXXXXX.rs 14:1]
regreset r: UInt<8>, clock_domain.clk, clock_domain.rst, UInt<8>(0h8) @[module-XXXXXXXXXX.rs 14:1]
connect m2.i, i @[module-XXXXXXXXXX.rs 15:1]
connect r, m2.o @[module-XXXXXXXXXX.rs 16:1]
wire _array_literal_expr: UInt<8>[3]