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change SimulationImpl::trace_memories to a BTreeMap for consistent iteration order

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Jacob Lifshay 2025-10-24 00:53:13 -07:00
parent b6e4cd0614
commit 838bd469ce
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
1 changed files with 2 additions and 2 deletions
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4
crates/fayalite/src/sim.rs
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@ -1522,7 +1522,7 @@ struct SimulationImpl {
state_ready_to_run: bool, state_ready_to_run: bool,
trace_decls: TraceModule, trace_decls: TraceModule,
traces: SimTraces<Box<[SimTrace<SimTraceKind, SimTraceState>]>>, traces: SimTraces<Box<[SimTrace<SimTraceKind, SimTraceState>]>>,
trace_memories: HashMap<StatePartIndex<StatePartKindMemories>, TraceMem>, trace_memories: BTreeMap<StatePartIndex<StatePartKindMemories>, TraceMem>,
trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>, trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
instant: SimInstant, instant: SimInstant,
clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>, clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
@ -1622,7 +1622,7 @@ impl SimulationImpl {
last_state: kind.make_state(), last_state: kind.make_state(),
}, },
))), ))),
trace_memories: HashMap::from_iter(compiled.trace_memories.iter().copied()), trace_memories: BTreeMap::from_iter(compiled.trace_memories.iter().copied()),
trace_writers: vec![], trace_writers: vec![],
instant: SimInstant::START, instant: SimInstant::START,
clocks_triggered: compiled.clocks_triggered, clocks_triggered: compiled.clocks_triggered,