add test for cfgs

crates/fayalite/build.rs

@@ -5,6 +5,8 @@ use std::{env, fs, path::Path};
 
 fn main() {
     println!("cargo::rustc-check-cfg=cfg(todo)");
+    println!("cargo::rustc-check-cfg=cfg(cfg_false_for_tests)");
+    println!("cargo::rustc-cfg=cfg_true_for_tests");
     let path = "visit_types.json";
     println!("cargo::rerun-if-changed={path}");
     println!("cargo::rerun-if-changed=build.rs");

crates/fayalite/tests/module.rs

@@ -4287,3 +4287,78 @@ circuit check_deduce_resets:
 ",
     };
 }
+
+#[hdl_module(outline_generated)]
+pub fn check_cfgs<#[cfg(cfg_false_for_tests)] A, #[cfg(cfg_true_for_tests)] B>(
+    #[cfg(cfg_false_for_tests)] a: A,
+    #[cfg(cfg_true_for_tests)] b: B,
+) {
+    #[hdl]
+    struct S<#[cfg(cfg_false_for_tests)] A, #[cfg(cfg_true_for_tests)] B> {
+        #[cfg(cfg_false_for_tests)]
+        a: A,
+        #[cfg(cfg_true_for_tests)]
+        b: B,
+    }
+    #[hdl]
+    #[cfg(cfg_false_for_tests)]
+    let i_a: A = m.input(a);
+    #[hdl]
+    #[cfg(cfg_true_for_tests)]
+    let i_b: B = m.input(b);
+    #[hdl]
+    let w: S<UInt<8>> = wire();
+    #[cfg(cfg_false_for_tests)]
+    {
+        #[hdl]
+        let o_a: A = m.output(a);
+        connect(o_a, w.a.cast_bits_to(a));
+        connect(w.a, i_a.cast_to_bits(UInt::new_static()));
+    }
+    #[cfg(cfg_true_for_tests)]
+    {
+        #[hdl]
+        let o_a: B = m.output(b);
+        connect(o_b, w.b.cast_bits_to(b));
+        connect(w.b, i_b.cast_to_bits(UInt::new_static()));
+    }
+}
+
+#[test]
+fn test_cfgs() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_cfgs(UInt::<8>);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: Reset}
+    type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+}