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WIP: use HdlOption[the_type_var] or UInt[123 + n] for creating types
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This commit is contained in:
Jacob Lifshay 2024-08-07 03:16:29 -07:00
parent cd99dbc849
commit 5835b995a9
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
63 changed files with 13500 additions and 13210 deletions
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24
crates/fayalite/examples/blinky.rs
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@ -1,11 +1,5 @@
use clap::Parser;
use fayalite::{
cli,
clock::{Clock, ClockDomain},
hdl_module,
int::{DynUInt, DynUIntType, IntCmp, IntTypeTrait, UInt},
reset::{SyncReset, ToReset},
};
use fayalite::{cli, prelude::*};
#[hdl_module]
fn blinky(clock_frequency: u64) {
@ -19,21 +13,21 @@ fn blinky(clock_frequency: u64) {
rst: rst.to_reset(),
};
let max_value = clock_frequency / 2 - 1;
let int_ty = DynUIntType::range_inclusive(0..=max_value);
let int_ty = UInt::range_inclusive(0..=max_value);
#[hdl]
let counter: DynUInt = m.reg_builder().clock_domain(cd).reset(int_ty.literal(0));
let counter: UInt = reg_builder().clock_domain(cd).reset(0u8.cast_to(int_ty));
#[hdl]
let output_reg: UInt<1> = m.reg_builder().clock_domain(cd).reset_default();
let output_reg: Bool = reg_builder().clock_domain(cd).reset(false);
#[hdl]
if counter.cmp_eq(max_value) {
m.connect_any(counter, 0u8);
m.connect(output_reg, !output_reg);
connect_any(counter, 0u8);
connect(output_reg, !output_reg);
} else {
m.connect_any(counter, counter + 1_hdl_u1);
connect_any(counter, counter + 1_hdl_u1);
}
#[hdl]
let led: UInt<1> = m.output();
m.connect(led, output_reg);
let led: Bool = m.output();
connect(led, output_reg);
}
#[derive(Parser)]