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Gather the FIFO debug ports in a bundle
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This commit is contained in:
Cesar Strauss 2024-12-29 13:17:24 -03:00
parent dcf865caec
commit 3771cea78e
Signed by: cesar
SSH key fingerprint: SHA256:sJUl6USz0D6c6sAQyFZab8XNPJnT05pt2ES0Lv/hCg4
1 changed files with 22 additions and 18 deletions
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40
crates/fayalite/src/util/ready_valid.rs
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@ -49,6 +49,18 @@ impl<T: Type> ReadyValid<T> {
} }
} }
/// This debug port is only meant to assist the formal proof of the queue.
#[cfg(test)]
#[doc(hidden)]
#[hdl]
pub struct QueueDebugPort<Element, Index> {
#[hdl(flip)]
index_to_check: Index,
stored: Element,
inp_index: Index,
out_index: Index,
}
#[hdl_module] #[hdl_module]
pub fn queue<T: Type>( pub fn queue<T: Type>(
ty: T, ty: T,
@ -180,27 +192,19 @@ pub fn queue<T: Type>(
} }
// These debug ports expose some internal state during the Induction phase // These debug ports expose some internal state during the Induction phase
// of Formal Verification. They are not present in normal use. // of Formal Verification. They are not present in normal use.
//
// TODO: gather the new debug ports in a bundle
#[cfg(test)] #[cfg(test)]
{ {
#[hdl]
let dbg: QueueDebugPort<T, UInt> = m.output(QueueDebugPort[ty][index_ty]);
// read the memory word currently stored at some fixed index // read the memory word currently stored at some fixed index
let debug_port = mem.new_read_port(); let debug_port = mem.new_read_port();
#[hdl] connect(debug_port.addr, dbg.index_to_check);
let dbg_index_to_check: UInt = m.input(index_ty);
#[hdl]
let dbg_stored: T = m.output(ty);
connect(debug_port.addr, dbg_index_to_check);
connect(debug_port.en, true); connect(debug_port.en, true);
connect(debug_port.clk, cd.clk); connect(debug_port.clk, cd.clk);
connect(dbg_stored, debug_port.data); connect(dbg.stored, debug_port.data);
// also expose the current read and write indices // also expose the current read and write indices
#[hdl] connect(dbg.inp_index, inp_index_reg);
let dbg_inp_index: UInt = m.output(index_ty); connect(dbg.out_index, out_index_reg);
#[hdl]
let dbg_out_index: UInt = m.output(index_ty);
connect(dbg_inp_index, inp_index_reg);
connect(dbg_out_index, out_index_reg);
} }
} }
@ -412,15 +416,15 @@ mod tests {
// sync the holding register, when it's occupied, to the // sync the holding register, when it's occupied, to the
// corresponding entry in the FIFO's circular buffer // corresponding entry in the FIFO's circular buffer
connect(dut.dbg_index_to_check, index_to_check); connect(dut.dbg.index_to_check, index_to_check);
#[hdl] #[hdl]
if let HdlSome(stored) = stored_reg { if let HdlSome(stored) = stored_reg {
hdl_assert(clk, stored.cmp_eq(dut.dbg_stored), ""); hdl_assert(clk, stored.cmp_eq(dut.dbg.stored), "");
} }
// sync the read and write indices // sync the read and write indices
hdl_assert(clk, inp_index_reg.cmp_eq(dut.dbg_inp_index), ""); hdl_assert(clk, inp_index_reg.cmp_eq(dut.dbg.inp_index), "");
hdl_assert(clk, out_index_reg.cmp_eq(dut.dbg_out_index), ""); hdl_assert(clk, out_index_reg.cmp_eq(dut.dbg.out_index), "");
// the indices should never go past the capacity, but induction // the indices should never go past the capacity, but induction
// doesn't know that... // doesn't know that...