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change NameId to have an opaque Id so output firrtl doesn't depend on how many modules of the same name were ever created
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This commit is contained in:
Jacob Lifshay 2024-10-07 19:06:01 -07:00
parent eed0afc6ab
commit 30b9a5e48d
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
6 changed files with 204 additions and 279 deletions
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35
crates/fayalite/src/firrtl.rs
View file

@ -27,7 +27,7 @@ use crate::{
simplify_memories::simplify_memories, simplify_memories::simplify_memories,
}, },
AnnotatedModuleIO, Block, ExternModuleBody, ExternModuleParameter, AnnotatedModuleIO, Block, ExternModuleBody, ExternModuleParameter,
ExternModuleParameterValue, Module, ModuleBody, NameId, NormalModuleBody, Stmt, ExternModuleParameterValue, Module, ModuleBody, NameOptId, NormalModuleBody, Stmt,
StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg,
StmtWire, StmtWire,
}, },
@ -187,9 +187,9 @@ struct NameMaker {
} }
impl NameMaker { impl NameMaker {
fn make(&mut self, name: NameId) -> Ident { fn make(&mut self, name: impl Into<String>) -> Ident {
let mut num: usize = name.1; let mut num = 0usize;
let name = String::from(&*name.0); let name: String = name.into();
// remove all invalid characters -- all valid characters are ASCII, so we can just remove invalid bytes // remove all invalid characters -- all valid characters are ASCII, so we can just remove invalid bytes
let mut name = String::from_iter( let mut name = String::from_iter(
name.bytes() name.bytes()
@ -221,7 +221,7 @@ impl NameMaker {
#[derive(Default)] #[derive(Default)]
struct Namespace { struct Namespace {
name_maker: NameMaker, name_maker: NameMaker,
map: HashMap<NameId, Ident>, map: HashMap<NameOptId, Ident>,
} }
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
@ -247,10 +247,11 @@ impl From<PortName> for Ident {
} }
impl Namespace { impl Namespace {
fn get(&mut self, name: NameId) -> Ident { fn get(&mut self, name: impl Into<NameOptId>) -> Ident {
let name: NameOptId = name.into();
#[cold] #[cold]
fn make(name_maker: &mut NameMaker, name: NameId) -> Ident { fn make(name_maker: &mut NameMaker, name: NameOptId) -> Ident {
name_maker.make(name) name_maker.make(name.0)
} }
*self *self
.map .map
@ -258,7 +259,7 @@ impl Namespace {
.or_insert_with(|| make(&mut self.name_maker, name)) .or_insert_with(|| make(&mut self.name_maker, name))
} }
fn make_new(&mut self, prefix: &str) -> Ident { fn make_new(&mut self, prefix: &str) -> Ident {
self.name_maker.make(NameId(prefix.intern(), 0)) self.name_maker.make(prefix)
} }
} }
@ -368,7 +369,7 @@ impl TypeState {
Ident(Intern::intern_owned(format!("Ty{id}"))) Ident(Intern::intern_owned(format!("Ty{id}")))
} }
fn get_bundle_field(&mut self, ty: Bundle, name: Interned<str>) -> Ident { fn get_bundle_field(&mut self, ty: Bundle, name: Interned<str>) -> Ident {
self.bundle_ns(ty).borrow_mut().get(NameId(name, 0)) self.bundle_ns(ty).borrow_mut().get(name)
} }
fn bundle_def(&self, ty: Bundle) -> (Ident, Rc<RefCell<Namespace>>) { fn bundle_def(&self, ty: Bundle) -> (Ident, Rc<RefCell<Namespace>>) {
self.bundle_defs.get_or_make(ty, |&ty, definitions| { self.bundle_defs.get_or_make(ty, |&ty, definitions| {
@ -382,7 +383,7 @@ impl TypeState {
if flipped { if flipped {
body.push_str("flip "); body.push_str("flip ");
} }
write!(body, "{}: ", ns.get(NameId(name, 0))).unwrap(); write!(body, "{}: ", ns.get(name)).unwrap();
body.push_str(&self.ty(ty)); body.push_str(&self.ty(ty));
} }
body.push('}'); body.push('}');
@ -406,7 +407,7 @@ impl TypeState {
for EnumVariant { name, ty } in ty.variants() { for EnumVariant { name, ty } in ty.variants() {
body.push_str(separator); body.push_str(separator);
separator = ", "; separator = ", ";
write!(body, "{}", variants.get(NameId(name, 0))).unwrap(); write!(body, "{}", variants.get(name)).unwrap();
if let Some(ty) = ty { if let Some(ty) = ty {
body.push_str(": "); body.push_str(": ");
body.push_str(&self.ty(ty)); body.push_str(&self.ty(ty));
@ -428,11 +429,7 @@ impl TypeState {
self.enum_def(ty).0 self.enum_def(ty).0
} }
fn get_enum_variant(&mut self, ty: Enum, name: Interned<str>) -> Ident { fn get_enum_variant(&mut self, ty: Enum, name: Interned<str>) -> Ident {
self.enum_def(ty) self.enum_def(ty).1.variants.borrow_mut().get(name)
.1
.variants
.borrow_mut()
.get(NameId(name, 0))
} }
fn ty<T: Type>(&self, ty: T) -> String { fn ty<T: Type>(&self, ty: T) -> String {
match ty.canonical() { match ty.canonical() {
@ -929,7 +926,7 @@ impl<'a> Exporter<'a> {
) in expr.field_values().into_iter().zip(ty.fields()) ) in expr.field_values().into_iter().zip(ty.fields())
{ {
debug_assert!(!flipped, "can't have bundle literal with flipped field -- this should have been caught in BundleLiteral::new_unchecked"); debug_assert!(!flipped, "can't have bundle literal with flipped field -- this should have been caught in BundleLiteral::new_unchecked");
let name = bundle_ns.borrow_mut().get(NameId(name, 0)); let name = bundle_ns.borrow_mut().get(name);
let field_value = self.expr(Expr::canonical(field_value), definitions, const_ty); let field_value = self.expr(Expr::canonical(field_value), definitions, const_ty);
definitions.add_definition_line(format_args!("connect {ident}.{name}, {field_value}")); definitions.add_definition_line(format_args!("connect {ident}.{name}, {field_value}"));
} }
@ -2199,7 +2196,7 @@ impl<'a> Exporter<'a> {
} in module.module_io().iter() } in module.module_io().iter()
{ {
self.targeted_annotations(module_name, vec![], annotations); self.targeted_annotations(module_name, vec![], annotations);
let name = self.module.ns.get(NameId(module_io.name(), 0)); let name = self.module.ns.get(module_io.name_id());
let ty = self.type_state.ty(module_io.ty()); let ty = self.type_state.ty(module_io.ty());
if module_io.is_input() { if module_io.is_input() {
writeln!( writeln!(

194
crates/fayalite/src/module.rs
View file

@ -36,9 +36,10 @@ use std::{
iter::FusedIterator, iter::FusedIterator,
marker::PhantomData, marker::PhantomData,
mem, mem,
num::NonZeroU64,
ops::Deref, ops::Deref,
rc::Rc, rc::Rc,
sync::Mutex, sync::atomic::AtomicU64,
}; };
pub mod transform; pub mod transform;
@ -602,8 +603,48 @@ impl BlockStack {
} }
} }
#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
pub struct Id(NonZeroU64);
impl Id {
pub fn new() -> Self {
static NEXT_ID: AtomicU64 = AtomicU64::new(1);
Self(
NonZeroU64::new(NEXT_ID.fetch_add(1, std::sync::atomic::Ordering::Relaxed))
.expect("Id::new ran out of ids"),
)
}
}
#[derive(Copy, Clone, Eq, PartialEq, Hash)] #[derive(Copy, Clone, Eq, PartialEq, Hash)]
pub struct NameId(pub Interned<str>, pub usize); pub struct NameOptId(pub Interned<str>, pub Option<Id>);
impl fmt::Debug for NameOptId {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
fmt::Display::fmt(self, f)
}
}
impl fmt::Display for NameOptId {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
f.write_str(&self.0)
}
}
impl From<Interned<str>> for NameOptId {
fn from(name: Interned<str>) -> Self {
Self(name, None)
}
}
impl From<NameId> for NameOptId {
fn from(name_id: NameId) -> Self {
Self(name_id.0, Some(name_id.1))
}
}
#[derive(Copy, Clone, Eq, PartialEq, Hash)]
pub struct NameId(pub Interned<str>, pub Id);
impl fmt::Debug for NameId { impl fmt::Debug for NameId {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
@ -613,13 +654,7 @@ impl fmt::Debug for NameId {
impl fmt::Display for NameId { impl fmt::Display for NameId {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
if self.0.is_empty() {
write!(f, "{}", self.1)
} else if self.1 == 0 {
f.write_str(&self.0) f.write_str(&self.0)
} else {
write!(f, "{}_{}", self.0, self.1)
}
} }
} }
@ -648,106 +683,6 @@ impl fmt::Debug for TargetName {
} }
} }
#[derive(Default)]
pub struct NameIdGen(HashMap<Interned<str>, usize>);
impl NameIdGen {
pub fn gen(&mut self, name: Interned<str>) -> NameId {
let next_id = self.0.entry(name).or_default();
let id = *next_id;
*next_id += 1;
NameId(name, id)
}
pub fn mark_as_used(&mut self, name_id: NameId) {
let next_id = self.0.entry(name_id.0).or_default();
*next_id = (*next_id).max(name_id.1 + 1);
}
pub fn for_module(module: Module<Bundle>) -> Self {
let mut retval = Self::default();
let Module {
name: _,
source_location: _,
body,
io_ty: _,
module_io,
module_annotations: _,
} = module;
for module_io in &module_io {
retval.mark_as_used(module_io.module_io.name_id());
}
match body {
ModuleBody::Extern(ExternModuleBody {
verilog_name: _,
parameters: _,
}) => {}
ModuleBody::Normal(NormalModuleBody { body }) => {
let mut blocks = vec![body];
while let Some(block) = blocks.pop() {
let Block { memories, stmts } = block;
for memory in memories {
retval.mark_as_used(memory.scoped_name().1);
}
for stmt in &stmts {
blocks.extend_from_slice(stmt.sub_stmt_blocks());
match stmt {
Stmt::Connect(StmtConnect {
lhs: _,
rhs: _,
source_location: _,
})
| Stmt::Formal(StmtFormal {
kind: _,
clk: _,
pred: _,
en: _,
text: _,
source_location: _,
})
| Stmt::If(StmtIf {
cond: _,
source_location: _,
blocks: _,
})
| Stmt::Match(StmtMatch {
expr: _,
source_location: _,
blocks: _,
}) => {}
Stmt::Declaration(StmtDeclaration::Instance(StmtInstance {
annotations: _,
instance,
})) => {
retval.mark_as_used(instance.name_id());
}
Stmt::Declaration(StmtDeclaration::Reg(StmtReg {
annotations: _,
reg,
})) => {
retval.mark_as_used(reg.name_id());
}
Stmt::Declaration(StmtDeclaration::Wire(StmtWire {
annotations: _,
wire,
})) => {
retval.mark_as_used(wire.name_id());
}
}
}
}
}
}
retval
}
pub fn gen_module_name(name: Interned<str>) -> NameId {
static MODULE_NAME_GEN: Mutex<Option<NameIdGen>> = Mutex::new(None);
MODULE_NAME_GEN
.lock()
.unwrap()
.get_or_insert_with(NameIdGen::default)
.gen(name)
}
}
#[derive(Copy, Clone, Eq, PartialEq, Hash)] #[derive(Copy, Clone, Eq, PartialEq, Hash)]
pub struct Instance<T: BundleType> { pub struct Instance<T: BundleType> {
scoped_name: ScopedNameId, scoped_name: ScopedNameId,
@ -836,7 +771,6 @@ struct ModuleBuilderImpl {
body: ModuleBodyBuilding, body: ModuleBodyBuilding,
io: Vec<AnnotatedModuleIO<ModuleBuilding>>, io: Vec<AnnotatedModuleIO<ModuleBuilding>>,
io_indexes: HashMap<ModuleIO<CanonicalType>, usize>, io_indexes: HashMap<ModuleIO<CanonicalType>, usize>,
name_id_gen: NameIdGen,
module_annotations: Vec<Annotation>, module_annotations: Vec<Annotation>,
} }
@ -1941,9 +1875,7 @@ impl<T: Type> RegBuilder<Expr<ClockDomain>, Option<Expr<T>>, T> {
ty, ty,
} = self; } = self;
ModuleBuilder::with(|module_builder| { ModuleBuilder::with(|module_builder| {
let mut impl_ = module_builder.impl_.borrow_mut(); let scoped_name = ScopedNameId(module_builder.name, NameId(name, Id::new()));
let scoped_name = ScopedNameId(module_builder.name, impl_.name_id_gen.gen(name));
drop(impl_);
let reg = Reg::new_unchecked(scoped_name, source_location, ty, clock_domain, init); let reg = Reg::new_unchecked(scoped_name, source_location, ty, clock_domain, init);
let retval = reg.to_expr(); let retval = reg.to_expr();
// convert before borrow_mut since ModuleBuilder could be reentered by T::canonical() // convert before borrow_mut since ModuleBuilder could be reentered by T::canonical()
@ -1991,8 +1923,13 @@ impl ModuleBuilder {
is_input: bool, is_input: bool,
ty: IO, ty: IO,
) -> Expr<IO> { ) -> Expr<IO> {
let module_io = let module_io = ModuleIO::<IO>::new_unchecked(
ModuleIO::<IO>::new_unchecked(self.name, name.intern(), source_location, is_input, ty); self.name,
NameId(name.intern(), Id::new()),
source_location,
is_input,
ty,
);
let retval = module_io.to_expr(); let retval = module_io.to_expr();
let module_io = module_io.canonical(); let module_io = module_io.canonical();
let mut impl_ = self.impl_.borrow_mut(); let mut impl_ = self.impl_.borrow_mut();
@ -2080,7 +2017,7 @@ impl ModuleBuilder {
module_kind: ModuleKind, module_kind: ModuleKind,
f: impl FnOnce(&Self) -> Result<(), E>, f: impl FnOnce(&Self) -> Result<(), E>,
) -> Result<Interned<Module<T>>, E> { ) -> Result<Interned<Module<T>>, E> {
let name = NameIdGen::gen_module_name(name.intern()); let name = NameId(name.intern(), Id::new());
let body = match module_kind { let body = match module_kind {
ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody { ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody {
verilog_name: name.0, verilog_name: name.0,
@ -2105,7 +2042,6 @@ impl ModuleBuilder {
body, body,
io: vec![], io: vec![],
io_indexes: HashMap::new(), io_indexes: HashMap::new(),
name_id_gen: NameIdGen::default(),
module_annotations: vec![], module_annotations: vec![],
}), }),
}; };
@ -2277,9 +2213,7 @@ pub fn annotate<T: Type>(target: Expr<T>, annotations: impl IntoAnnotations) {
#[track_caller] #[track_caller]
pub fn wire_with_loc<T: Type>(name: &str, source_location: SourceLocation, ty: T) -> Expr<T> { pub fn wire_with_loc<T: Type>(name: &str, source_location: SourceLocation, ty: T) -> Expr<T> {
ModuleBuilder::with(|m| { ModuleBuilder::with(|m| {
let mut impl_ = m.impl_.borrow_mut(); let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
drop(impl_);
let wire = Wire::<T>::new_unchecked(scoped_name, source_location, ty); let wire = Wire::<T>::new_unchecked(scoped_name, source_location, ty);
let retval = wire.to_expr(); let retval = wire.to_expr();
let canonical_wire = wire.canonical(); let canonical_wire = wire.canonical();
@ -2311,9 +2245,7 @@ fn incomplete_declaration(
source_location: SourceLocation, source_location: SourceLocation,
) -> Rc<RefCell<IncompleteDeclaration>> { ) -> Rc<RefCell<IncompleteDeclaration>> {
ModuleBuilder::with(|m| { ModuleBuilder::with(|m| {
let mut impl_ = m.impl_.borrow_mut(); let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
drop(impl_);
let retval = Rc::new(RefCell::new(IncompleteDeclaration::Incomplete { let retval = Rc::new(RefCell::new(IncompleteDeclaration::Incomplete {
name: scoped_name, name: scoped_name,
source_location, source_location,
@ -2489,9 +2421,7 @@ pub fn instance_with_loc<T: BundleType>(
source_location: SourceLocation, source_location: SourceLocation,
) -> Expr<T> { ) -> Expr<T> {
ModuleBuilder::with(|m| { ModuleBuilder::with(|m| {
let mut impl_ = m.impl_.borrow_mut(); let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
drop(impl_);
let instance = Instance::<T> { let instance = Instance::<T> {
scoped_name, scoped_name,
instantiated, instantiated,
@ -2530,9 +2460,7 @@ fn memory_impl<Element: Type, Len: Size>(
source_location: SourceLocation, source_location: SourceLocation,
) -> MemBuilder<Element, Len> { ) -> MemBuilder<Element, Len> {
ModuleBuilder::with(|m| { ModuleBuilder::with(|m| {
let mut impl_ = m.impl_.borrow_mut(); let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
drop(impl_);
let (retval, target_mem) = MemBuilder::new(scoped_name, source_location, mem_element_type); let (retval, target_mem) = MemBuilder::new(scoped_name, source_location, mem_element_type);
let mut impl_ = m.impl_.borrow_mut(); let mut impl_ = m.impl_.borrow_mut();
let body = impl_.body.builder_normal_body(); let body = impl_.body.builder_normal_body();
@ -2608,6 +2536,7 @@ pub fn memory<Element: Type>(
pub struct ModuleIO<T: Type> { pub struct ModuleIO<T: Type> {
containing_module_name: NameId, containing_module_name: NameId,
bundle_field: BundleField, bundle_field: BundleField,
id: Id,
ty: T, ty: T,
source_location: SourceLocation, source_location: SourceLocation,
} }
@ -2627,12 +2556,14 @@ impl<T: Type> ModuleIO<T> {
let Self { let Self {
containing_module_name, containing_module_name,
bundle_field, bundle_field,
id,
ty: _, ty: _,
source_location, source_location,
} = *self; } = *self;
ModuleIO { ModuleIO {
containing_module_name, containing_module_name,
bundle_field, bundle_field,
id,
ty: bundle_field.ty, ty: bundle_field.ty,
source_location, source_location,
} }
@ -2656,7 +2587,7 @@ impl<T: Type> ModuleIO<T> {
self.bundle_field.name self.bundle_field.name
} }
pub fn name_id(&self) -> NameId { pub fn name_id(&self) -> NameId {
NameId(self.bundle_field.name, 0) NameId(self.bundle_field.name, self.id)
} }
pub fn scoped_name(&self) -> ScopedNameId { pub fn scoped_name(&self) -> ScopedNameId {
ScopedNameId(self.containing_module_name, self.name_id()) ScopedNameId(self.containing_module_name, self.name_id())
@ -2666,7 +2597,7 @@ impl<T: Type> ModuleIO<T> {
} }
pub fn new_unchecked( pub fn new_unchecked(
containing_module_name: NameId, containing_module_name: NameId,
name: Interned<str>, name: NameId,
source_location: SourceLocation, source_location: SourceLocation,
is_input: bool, is_input: bool,
ty: T, ty: T,
@ -2674,10 +2605,11 @@ impl<T: Type> ModuleIO<T> {
Self { Self {
containing_module_name, containing_module_name,
bundle_field: BundleField { bundle_field: BundleField {
name, name: name.0,
flipped: is_input, flipped: is_input,
ty: ty.canonical(), ty: ty.canonical(),
}, },
id: name.1,
ty, ty,
source_location, source_location,
} }

7
crates/fayalite/src/module/transform/simplify_enums.rs
View file

@ -14,8 +14,7 @@ use crate::{
memory::{DynPortType, Mem, MemPort}, memory::{DynPortType, Mem, MemPort},
module::{ module::{
transform::visit::{Fold, Folder}, transform::visit::{Fold, Folder},
Block, Module, NameId, NameIdGen, ScopedNameId, Stmt, StmtConnect, StmtIf, StmtMatch, Block, Id, Module, NameId, ScopedNameId, Stmt, StmtConnect, StmtIf, StmtMatch, StmtWire,
StmtWire,
}, },
source_location::SourceLocation, source_location::SourceLocation,
ty::{CanonicalType, Type}, ty::{CanonicalType, Type},
@ -92,13 +91,12 @@ enum EnumTypeState {
} }
struct ModuleState { struct ModuleState {
name_id_gen: NameIdGen,
module_name: NameId, module_name: NameId,
} }
impl ModuleState { impl ModuleState {
fn gen_name(&mut self, name: &str) -> ScopedNameId { fn gen_name(&mut self, name: &str) -> ScopedNameId {
ScopedNameId(self.module_name, self.name_id_gen.gen(name.intern())) ScopedNameId(self.module_name, NameId(name.intern(), Id::new()))
} }
} }
@ -632,7 +630,6 @@ impl Folder for State {
fn fold_module<T: BundleType>(&mut self, v: Module<T>) -> Result<Module<T>, Self::Error> { fn fold_module<T: BundleType>(&mut self, v: Module<T>) -> Result<Module<T>, Self::Error> {
self.module_state_stack.push(ModuleState { self.module_state_stack.push(ModuleState {
name_id_gen: NameIdGen::for_module(v.canonical()),
module_name: v.name_id(), module_name: v.name_id(),
}); });
let retval = Fold::default_fold(v, self); let retval = Fold::default_fold(v, self);

19
crates/fayalite/src/module/transform/simplify_memories.rs
View file

@ -10,7 +10,7 @@ use crate::{
memory::{Mem, MemPort, PortType}, memory::{Mem, MemPort, PortType},
module::{ module::{
transform::visit::{Fold, Folder}, transform::visit::{Fold, Folder},
Block, Module, NameId, NameIdGen, ScopedNameId, Stmt, StmtConnect, StmtWire, Block, Id, Module, NameId, ScopedNameId, Stmt, StmtConnect, StmtWire,
}, },
source_location::SourceLocation, source_location::SourceLocation,
ty::{CanonicalType, Type}, ty::{CanonicalType, Type},
@ -417,7 +417,6 @@ impl SplitMemState<'_, '_> {
struct ModuleState { struct ModuleState {
output_module: Option<Interned<Module<Bundle>>>, output_module: Option<Interned<Module<Bundle>>>,
name_id_gen: NameIdGen,
memories: HashMap<ScopedNameId, MemState>, memories: HashMap<ScopedNameId, MemState>,
} }
@ -626,10 +625,10 @@ impl ModuleState {
mem_name_path: &str, mem_name_path: &str,
split_state: &SplitState<'_>, split_state: &SplitState<'_>,
) -> Mem { ) -> Mem {
let mem_name = self.name_id_gen.gen(Intern::intern_owned(format!( let mem_name = NameId(
"{}{mem_name_path}", Intern::intern_owned(format!("{}{mem_name_path}", input_mem.scoped_name().1 .0)),
input_mem.scoped_name().1 .0 Id::new(),
))); );
let mem_name = ScopedNameId(input_mem.scoped_name().0, mem_name); let mem_name = ScopedNameId(input_mem.scoped_name().0, mem_name);
let output_element_type = match single_type { let output_element_type = match single_type {
SingleType::UInt(ty) => ty.canonical(), SingleType::UInt(ty) => ty.canonical(),
@ -753,9 +752,10 @@ impl ModuleState {
let port_ty = port.ty(); let port_ty = port.ty();
let NameId(mem_name, _) = input_mem.scoped_name().1; let NameId(mem_name, _) = input_mem.scoped_name().1;
let port_name = port.port_name(); let port_name = port.port_name();
let wire_name = self let wire_name = NameId(
.name_id_gen Intern::intern_owned(format!("{mem_name}_{port_name}")),
.gen(Intern::intern_owned(format!("{mem_name}_{port_name}"))); Id::new(),
);
let wire = Wire::new_unchecked( let wire = Wire::new_unchecked(
ScopedNameId(input_mem.scoped_name().0, wire_name), ScopedNameId(input_mem.scoped_name().0, wire_name),
port.source_location(), port.source_location(),
@ -887,7 +887,6 @@ impl Folder for State {
module, module,
ModuleState { ModuleState {
output_module: None, output_module: None,
name_id_gen: NameIdGen::for_module(*module),
memories: HashMap::new(), memories: HashMap::new(),
}, },
); );

224
crates/fayalite/tests/module.rs
View file

@ -175,9 +175,9 @@ circuit check_array_repeat:
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
assert_export_firrtl! { assert_export_firrtl! {
m => m =>
"/test/check_array_repeat_1.fir": r"FIRRTL version 3.2.0 "/test/check_array_repeat.fir": r"FIRRTL version 3.2.0
circuit check_array_repeat_1: circuit check_array_repeat:
module check_array_repeat_1: @[module-XXXXXXXXXX.rs 1:1] module check_array_repeat: @[module-XXXXXXXXXX.rs 1:1]
input i: UInt<8> @[module-XXXXXXXXXX.rs 2:1] input i: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
output o: UInt<8>[4] @[module-XXXXXXXXXX.rs 3:1] output o: UInt<8>[4] @[module-XXXXXXXXXX.rs 3:1]
wire _array_literal_expr: UInt<8>[4] wire _array_literal_expr: UInt<8>[4]
@ -1672,9 +1672,9 @@ fn test_memory_of_arrays() {
circuit check_memory_of_arrays: %[[ circuit check_memory_of_arrays: %[[
{ {
"class": "firrtl.annotations.MemoryFileInlineAnnotation", "class": "firrtl.annotations.MemoryFileInlineAnnotation",
"filename": "/test/check_memory_of_arrays/mem_1.mem", "filename": "/test/check_memory_of_arrays/mem.mem",
"hexOrBinary": "h", "hexOrBinary": "h",
"target": "~check_memory_of_arrays|check_memory_of_arrays>mem_1" "target": "~check_memory_of_arrays|check_memory_of_arrays>mem"
} }
]] ]]
type Ty0 = {addr: UInt<4>, en: UInt<1>, clk: Clock, flip data: UInt<8>[2][3]} type Ty0 = {addr: UInt<4>, en: UInt<1>, clk: Clock, flip data: UInt<8>[2][3]}
@ -1688,7 +1688,7 @@ circuit check_memory_of_arrays: %[[
input wdata: UInt<8>[2][3] @[module-XXXXXXXXXX.rs 5:1] input wdata: UInt<8>[2][3] @[module-XXXXXXXXXX.rs 5:1]
input wmask: UInt<1>[2][3] @[module-XXXXXXXXXX.rs 6:1] input wmask: UInt<1>[2][3] @[module-XXXXXXXXXX.rs 6:1]
input clk: Clock @[module-XXXXXXXXXX.rs 7:1] input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
mem mem_1: @[module-XXXXXXXXXX.rs 8:1] mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
data-type => UInt<8>[6] data-type => UInt<8>[6]
depth => 16 depth => 16
read-latency => 0 read-latency => 0
@ -1698,30 +1698,30 @@ circuit check_memory_of_arrays: %[[
writer => w1 writer => w1
wire mem_r0: Ty0 @[module-XXXXXXXXXX.rs 9:1] wire mem_r0: Ty0 @[module-XXXXXXXXXX.rs 9:1]
wire mem_w1: Ty1 @[module-XXXXXXXXXX.rs 14:1] wire mem_w1: Ty1 @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.data[0][0], mem_1.r0.data[0] @[module-XXXXXXXXXX.rs 9:1] connect mem_r0.data[0][0], `mem`.r0.data[0] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[0][1], mem_1.r0.data[1] @[module-XXXXXXXXXX.rs 9:1] connect mem_r0.data[0][1], `mem`.r0.data[1] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[1][0], mem_1.r0.data[2] @[module-XXXXXXXXXX.rs 9:1] connect mem_r0.data[1][0], `mem`.r0.data[2] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[1][1], mem_1.r0.data[3] @[module-XXXXXXXXXX.rs 9:1] connect mem_r0.data[1][1], `mem`.r0.data[3] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[2][0], mem_1.r0.data[4] @[module-XXXXXXXXXX.rs 9:1] connect mem_r0.data[2][0], `mem`.r0.data[4] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[2][1], mem_1.r0.data[5] @[module-XXXXXXXXXX.rs 9:1] connect mem_r0.data[2][1], `mem`.r0.data[5] @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.w1.data[0], mem_w1.data[0][0] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.data[0], mem_w1.data[0][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[0], mem_w1.mask[0][0] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.mask[0], mem_w1.mask[0][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.data[1], mem_w1.data[0][1] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.data[1], mem_w1.data[0][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[1], mem_w1.mask[0][1] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.mask[1], mem_w1.mask[0][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.data[2], mem_w1.data[1][0] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.data[2], mem_w1.data[1][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[2], mem_w1.mask[1][0] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.mask[2], mem_w1.mask[1][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.data[3], mem_w1.data[1][1] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.data[3], mem_w1.data[1][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[3], mem_w1.mask[1][1] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.mask[3], mem_w1.mask[1][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.data[4], mem_w1.data[2][0] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.data[4], mem_w1.data[2][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[4], mem_w1.mask[2][0] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.mask[4], mem_w1.mask[2][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.data[5], mem_w1.data[2][1] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.data[5], mem_w1.data[2][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[5], mem_w1.mask[2][1] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.mask[5], mem_w1.mask[2][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1] connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1] connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1] connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1] connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1] connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1] connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
@ -1732,7 +1732,7 @@ circuit check_memory_of_arrays: %[[
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1] connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1] connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
"#, "#,
"/test/check_memory_of_arrays/mem_1.mem": r"000000000000 "/test/check_memory_of_arrays/mem.mem": r"000000000000
020103020101 020103020101
04080c080402 04080c080402
061b1b120903 061b1b120903
@ -2445,9 +2445,9 @@ fn test_memory_of_enum() {
circuit check_memory_of_enum: %[[ circuit check_memory_of_enum: %[[
{ {
"class": "firrtl.annotations.MemoryFileInlineAnnotation", "class": "firrtl.annotations.MemoryFileInlineAnnotation",
"filename": "/test/check_memory_of_enum/mem_1.mem", "filename": "/test/check_memory_of_enum/mem.mem",
"hexOrBinary": "b", "hexOrBinary": "b",
"target": "~check_memory_of_enum|check_memory_of_enum>mem_1" "target": "~check_memory_of_enum|check_memory_of_enum>mem"
} }
]] ]]
type Ty0 = {|A, B: UInt<8>, C: UInt<1>[3]|} type Ty0 = {|A, B: UInt<8>, C: UInt<1>[3]|}
@ -2462,7 +2462,7 @@ circuit check_memory_of_enum: %[[
input wdata: Ty0 @[module-XXXXXXXXXX.rs 5:1] input wdata: Ty0 @[module-XXXXXXXXXX.rs 5:1]
input wmask: UInt<1> @[module-XXXXXXXXXX.rs 6:1] input wmask: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
input clk: Clock @[module-XXXXXXXXXX.rs 7:1] input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
mem mem_1: @[module-XXXXXXXXXX.rs 8:1] mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
data-type => UInt<10> data-type => UInt<10>
depth => 16 depth => 16
read-latency => 0 read-latency => 0
@ -2474,10 +2474,10 @@ circuit check_memory_of_enum: %[[
wire mem_w1: Ty2 @[module-XXXXXXXXXX.rs 14:1] wire mem_w1: Ty2 @[module-XXXXXXXXXX.rs 14:1]
wire _cast_bits_to_enum_expr: Ty0 wire _cast_bits_to_enum_expr: Ty0
wire _cast_bits_to_enum_expr_body: UInt<8> wire _cast_bits_to_enum_expr_body: UInt<8>
connect _cast_bits_to_enum_expr_body, head(mem_1.r0.data, 8) connect _cast_bits_to_enum_expr_body, head(`mem`.r0.data, 8)
when eq(UInt<2>(0), tail(mem_1.r0.data, 8)): when eq(UInt<2>(0), tail(`mem`.r0.data, 8)):
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(A) connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
else when eq(UInt<2>(1), tail(mem_1.r0.data, 8)): else when eq(UInt<2>(1), tail(`mem`.r0.data, 8)):
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body) connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body)
else: else:
wire _cast_bits_to_array_expr: UInt<1>[3] wire _cast_bits_to_array_expr: UInt<1>[3]
@ -2504,14 +2504,14 @@ circuit check_memory_of_enum: %[[
wire _cast_to_bits_expr: UInt<3> wire _cast_to_bits_expr: UInt<3>
connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
connect _cast_enum_to_bits_expr, pad(cat(_cast_to_bits_expr, UInt<2>(2)), 10) connect _cast_enum_to_bits_expr, pad(cat(_cast_to_bits_expr, UInt<2>(2)), 10)
connect mem_1.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.mask, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1] connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1] connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1] connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
; connect different types: ; connect different types:
; lhs: UInt<4> ; lhs: UInt<4>
; rhs: UInt<8> ; rhs: UInt<8>
@ -2528,7 +2528,7 @@ circuit check_memory_of_enum: %[[
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1] connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1] connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
"#, "#,
"/test/check_memory_of_enum/mem_1.mem": r"0000000000 "/test/check_memory_of_enum/mem.mem": r"0000000000
0000000110 0000000110
0000001010 0000001010
0000010010 0000010010
@ -2602,7 +2602,7 @@ circuit check_memory_of_enum: %[[
reader => r0 reader => r0
writer => w1 writer => w1
wire mem_r0: Ty2 @[module-XXXXXXXXXX.rs 9:1] wire mem_r0: Ty2 @[module-XXXXXXXXXX.rs 9:1]
wire mem_w1_1: Ty4 @[module-XXXXXXXXXX.rs 14:1] wire mem_w1: Ty4 @[module-XXXXXXXXXX.rs 14:1]
wire _cast_bits_to_enum_expr: Ty0 wire _cast_bits_to_enum_expr: Ty0
when eq(UInt<2>(0), tail(mem_tag.r0.data, 0)): when eq(UInt<2>(0), tail(mem_tag.r0.data, 0)):
connect _cast_bits_to_enum_expr, {|A, B, C|}(A) connect _cast_bits_to_enum_expr, {|A, B, C|}(A)
@ -2612,7 +2612,7 @@ circuit check_memory_of_enum: %[[
connect _cast_bits_to_enum_expr, {|A, B, C|}(C) connect _cast_bits_to_enum_expr, {|A, B, C|}(C)
connect mem_r0.data.tag, _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 9:1] connect mem_r0.data.tag, _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 9:1]
wire _cast_enum_to_bits_expr: UInt<2> wire _cast_enum_to_bits_expr: UInt<2>
match mem_w1_1.data.tag: match mem_w1.data.tag:
A: A:
connect _cast_enum_to_bits_expr, UInt<2>(0) connect _cast_enum_to_bits_expr, UInt<2>(0)
B: B:
@ -2620,29 +2620,29 @@ circuit check_memory_of_enum: %[[
C: C:
connect _cast_enum_to_bits_expr, UInt<2>(2) connect _cast_enum_to_bits_expr, UInt<2>(2)
connect mem_tag.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1] connect mem_tag.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.mask, mem_w1_1.mask.tag @[module-XXXXXXXXXX.rs 14:1] connect mem_tag.w1.mask, mem_w1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1] connect mem_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1] connect mem_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1] connect mem_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1] connect mem_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1] connect mem_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1] connect mem_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.data.body, mem_body.r0.data @[module-XXXXXXXXXX.rs 9:1] connect mem_r0.data.body, mem_body.r0.data @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.w1.data, mem_w1_1.data.body @[module-XXXXXXXXXX.rs 14:1] connect mem_body.w1.data, mem_w1.data.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.mask, mem_w1_1.mask.body @[module-XXXXXXXXXX.rs 14:1] connect mem_body.w1.mask, mem_w1.mask.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1] connect mem_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1] connect mem_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1] connect mem_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1] connect mem_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1] connect mem_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1] connect mem_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
wire mem_w1: Ty9 @[module-XXXXXXXXXX.rs 14:1] wire mem_w1_1: Ty9 @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.data, mem_w1_1.data @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.mask.tag, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.mask.body, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
; connect different types: ; connect different types:
; lhs: UInt<4> ; lhs: UInt<4>
; rhs: UInt<8> ; rhs: UInt<8>
@ -2653,11 +2653,11 @@ circuit check_memory_of_enum: %[[
; connect different types: ; connect different types:
; lhs: UInt<4> ; lhs: UInt<4>
; rhs: UInt<8> ; rhs: UInt<8>
connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1] connect mem_w1_1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1] connect mem_w1_1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1] connect mem_w1_1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1] connect mem_w1_1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1] connect mem_w1_1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
"#, "#,
"/test/check_memory_of_enum/mem_body.mem": r"00 "/test/check_memory_of_enum/mem_body.mem": r"00
01 01
@ -2748,32 +2748,32 @@ circuit check_memory_of_enum: %[[
reader => r0 reader => r0
writer => w1 writer => w1
wire mem_r0: Ty1 @[module-XXXXXXXXXX.rs 9:1] wire mem_r0: Ty1 @[module-XXXXXXXXXX.rs 9:1]
wire mem_w1_1: Ty3 @[module-XXXXXXXXXX.rs 14:1] wire mem_w1: Ty3 @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.data.tag, mem_tag.r0.data @[module-XXXXXXXXXX.rs 9:1] connect mem_r0.data.tag, mem_tag.r0.data @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.w1.data, mem_w1_1.data.tag @[module-XXXXXXXXXX.rs 14:1] connect mem_tag.w1.data, mem_w1.data.tag @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.mask, mem_w1_1.mask.tag @[module-XXXXXXXXXX.rs 14:1] connect mem_tag.w1.mask, mem_w1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1] connect mem_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1] connect mem_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1] connect mem_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1] connect mem_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1] connect mem_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1] connect mem_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.data.body, mem_body.r0.data @[module-XXXXXXXXXX.rs 9:1] connect mem_r0.data.body, mem_body.r0.data @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.w1.data, mem_w1_1.data.body @[module-XXXXXXXXXX.rs 14:1] connect mem_body.w1.data, mem_w1.data.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.mask, mem_w1_1.mask.body @[module-XXXXXXXXXX.rs 14:1] connect mem_body.w1.mask, mem_w1.mask.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1] connect mem_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1] connect mem_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1] connect mem_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1] connect mem_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1] connect mem_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1] connect mem_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
wire mem_w1: Ty8 @[module-XXXXXXXXXX.rs 14:1] wire mem_w1_1: Ty8 @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.data, mem_w1_1.data @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.mask.tag, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1] connect mem_w1.mask.body, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
; connect different types: ; connect different types:
; lhs: UInt<4> ; lhs: UInt<4>
; rhs: UInt<8> ; rhs: UInt<8>
@ -2784,11 +2784,11 @@ circuit check_memory_of_enum: %[[
; connect different types: ; connect different types:
; lhs: UInt<4> ; lhs: UInt<4>
; rhs: UInt<8> ; rhs: UInt<8>
connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1] connect mem_w1_1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1] connect mem_w1_1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1] connect mem_w1_1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1] connect mem_w1_1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1] connect mem_w1_1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
"#, "#,
"/test/check_memory_of_enum/mem_body.mem": r"00 "/test/check_memory_of_enum/mem_body.mem": r"00
01 01
@ -2950,7 +2950,7 @@ circuit check_memory_of_array_of_enum:
input wdata: Ty0[2] @[module-XXXXXXXXXX.rs 5:1] input wdata: Ty0[2] @[module-XXXXXXXXXX.rs 5:1]
input wmask: UInt<1>[2] @[module-XXXXXXXXXX.rs 6:1] input wmask: UInt<1>[2] @[module-XXXXXXXXXX.rs 6:1]
input clk: Clock @[module-XXXXXXXXXX.rs 7:1] input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
mem mem_1: @[module-XXXXXXXXXX.rs 8:1] mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
data-type => UInt<10>[2] data-type => UInt<10>[2]
depth => 256 depth => 256
read-latency => 0 read-latency => 0
@ -2962,10 +2962,10 @@ circuit check_memory_of_array_of_enum:
wire mem_w1: Ty2 @[module-XXXXXXXXXX.rs 14:1] wire mem_w1: Ty2 @[module-XXXXXXXXXX.rs 14:1]
wire _cast_bits_to_enum_expr: Ty0 wire _cast_bits_to_enum_expr: Ty0
wire _cast_bits_to_enum_expr_body: UInt<8> wire _cast_bits_to_enum_expr_body: UInt<8>
connect _cast_bits_to_enum_expr_body, head(mem_1.r0.data[0], 8) connect _cast_bits_to_enum_expr_body, head(`mem`.r0.data[0], 8)
when eq(UInt<2>(0), tail(mem_1.r0.data[0], 8)): when eq(UInt<2>(0), tail(`mem`.r0.data[0], 8)):
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(A) connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
else when eq(UInt<2>(1), tail(mem_1.r0.data[0], 8)): else when eq(UInt<2>(1), tail(`mem`.r0.data[0], 8)):
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body) connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body)
else: else:
wire _cast_bits_to_array_expr: UInt<1>[3] wire _cast_bits_to_array_expr: UInt<1>[3]
@ -2980,10 +2980,10 @@ circuit check_memory_of_array_of_enum:
connect mem_r0.data[0], _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 9:1] connect mem_r0.data[0], _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 9:1]
wire _cast_bits_to_enum_expr_1: Ty0 wire _cast_bits_to_enum_expr_1: Ty0
wire _cast_bits_to_enum_expr_body_1: UInt<8> wire _cast_bits_to_enum_expr_body_1: UInt<8>
connect _cast_bits_to_enum_expr_body_1, head(mem_1.r0.data[1], 8) connect _cast_bits_to_enum_expr_body_1, head(`mem`.r0.data[1], 8)
when eq(UInt<2>(0), tail(mem_1.r0.data[1], 8)): when eq(UInt<2>(0), tail(`mem`.r0.data[1], 8)):
connect _cast_bits_to_enum_expr_1, {|A, B: UInt<8>, C: UInt<1>[3]|}(A) connect _cast_bits_to_enum_expr_1, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
else when eq(UInt<2>(1), tail(mem_1.r0.data[1], 8)): else when eq(UInt<2>(1), tail(`mem`.r0.data[1], 8)):
connect _cast_bits_to_enum_expr_1, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body_1) connect _cast_bits_to_enum_expr_1, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body_1)
else: else:
wire _cast_bits_to_array_expr_1: UInt<1>[3] wire _cast_bits_to_array_expr_1: UInt<1>[3]
@ -3010,8 +3010,8 @@ circuit check_memory_of_array_of_enum:
wire _cast_to_bits_expr: UInt<3> wire _cast_to_bits_expr: UInt<3>
connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
connect _cast_enum_to_bits_expr, pad(cat(_cast_to_bits_expr, UInt<2>(2)), 10) connect _cast_enum_to_bits_expr, pad(cat(_cast_to_bits_expr, UInt<2>(2)), 10)
connect mem_1.w1.data[0], _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.data[0], _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[0], mem_w1.mask[0] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.mask[0], mem_w1.mask[0] @[module-XXXXXXXXXX.rs 14:1]
wire _cast_enum_to_bits_expr_1: UInt<10> wire _cast_enum_to_bits_expr_1: UInt<10>
match mem_w1.data[1]: match mem_w1.data[1]:
A: A:
@ -3026,14 +3026,14 @@ circuit check_memory_of_array_of_enum:
wire _cast_to_bits_expr_1: UInt<3> wire _cast_to_bits_expr_1: UInt<3>
connect _cast_to_bits_expr_1, cat(_cast_array_to_bits_expr_1[2], cat(_cast_array_to_bits_expr_1[1], _cast_array_to_bits_expr_1[0])) connect _cast_to_bits_expr_1, cat(_cast_array_to_bits_expr_1[2], cat(_cast_array_to_bits_expr_1[1], _cast_array_to_bits_expr_1[0]))
connect _cast_enum_to_bits_expr_1, pad(cat(_cast_to_bits_expr_1, UInt<2>(2)), 10) connect _cast_enum_to_bits_expr_1, pad(cat(_cast_to_bits_expr_1, UInt<2>(2)), 10)
connect mem_1.w1.data[1], _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.data[1], _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[1], mem_w1.mask[1] @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.mask[1], mem_w1.mask[1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1] connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1] connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1] connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1] connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1] connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1] connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1] connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
@ -3344,11 +3344,11 @@ circuit check_uninit:
simplify_enums: None, simplify_enums: None,
..ExportOptions::default() ..ExportOptions::default()
}, },
"/test/check_uninit_1.fir": r"FIRRTL version 3.2.0 "/test/check_uninit.fir": r"FIRRTL version 3.2.0
circuit check_uninit_1: circuit check_uninit:
type Ty0 = {} type Ty0 = {}
type Ty1 = {|HdlNone, HdlSome: Ty0|} type Ty1 = {|HdlNone, HdlSome: Ty0|}
module check_uninit_1: @[module-XXXXXXXXXX.rs 1:1] module check_uninit: @[module-XXXXXXXXXX.rs 1:1]
output o: Ty1[3] @[module-XXXXXXXXXX.rs 2:1] output o: Ty1[3] @[module-XXXXXXXXXX.rs 2:1]
wire _uninit_expr: Ty1[3] wire _uninit_expr: Ty1[3]
invalidate _uninit_expr invalidate _uninit_expr

2
crates/fayalite/visit_types.json
View file

@ -28,7 +28,7 @@
"$kind": "Struct", "$kind": "Struct",
"$constructor": "ModuleIO::new_unchecked", "$constructor": "ModuleIO::new_unchecked",
"containing_module_name_id()": "Visible", "containing_module_name_id()": "Visible",
"name()": "Visible", "name_id()": "Visible",
"source_location()": "Visible", "source_location()": "Visible",
"is_input()": "Visible", "is_input()": "Visible",
"ty()": "Visible" "ty()": "Visible"